Top Level VHDL Code



-- simulate the relatively slow progress of an elevator car by dividing the

-- clock down by an outrageously high number and scanning the car registers for

-- an elevator s next

-- (normally the signals used below would be IO pins on the chip, but we have

-- no physical elevator, so this is a kind of "diagnostic mode")-Top Level VHDL Code



-- simulate the relatively slow progress of an elevator car by dividing the

　 -- clock down by an outrageously high number and scanning the car registers for

　 -- an elevator s next

　 -- (normally the signals used below would be IO pins on the chip, but we have

　 -- no physical elevator, so this is a kind of "diagnostic mode")