文件名称:74HC373
-
所属分类:
- 标签属性:
- 上传时间:2012-11-16
-
文件大小:358.82kb
-
已下载:0次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
74hc373 基于verilog语言的实现 -Verilog language 74hc373 based on the realization of
(系统自动生成,下载前可以参看下载内容)
下载文件列表
74hc373.pdf
74hc373/
74hc373/74hc373.prj
74hc373/component/
74hc373/constraint/
74hc373/coreconsole/
74hc373/designer/
74hc373/designer/impl1/
74hc373/designer/impl1/designer.log
74hc373/designer/impl1/latch8.adb
74hc373/designer/impl1/latch8.dtf/
74hc373/designer/impl1/latch8.dtf/verify.log
74hc373/designer/impl1/latch8.ide_des
74hc373/designer/impl1/latch8.pdb
74hc373/designer/impl1/latch8.pdb.depends
74hc373/designer/impl1/latch8.tcl
74hc373/designer/impl1/latch8_fp/
74hc373/designer/impl1/latch8_fp/$$FlashPro_07294.L$$
74hc373/designer/impl1/latch8_fp/latch8.log
74hc373/designer/impl1/latch8_fp/latch8.pro
74hc373/designer/impl1/latch8_fp/projectData/
74hc373/designer/impl1/latch8_fp/projectData/latch8.pdb
74hc373/designer/impl1/simulation/
74hc373/hdl/
74hc373/hdl/74hc373.v
74hc373/phy_synthesis/
74hc373/simulation/
74hc373/simulation/modelsim.ini
74hc373/simulation/modelsim.ini.sav
74hc373/simulation/modelsim.log
74hc373/simulation/presynth/
74hc373/simulation/presynth/latch8/
74hc373/simulation/presynth/latch8/verilog.psm
74hc373/simulation/presynth/latch8/_primary.dat
74hc373/simulation/presynth/latch8/_primary.dbs
74hc373/simulation/presynth/latch8/_primary.vhd
74hc373/simulation/presynth/testbench/
74hc373/simulation/presynth/testbench/verilog.psm
74hc373/simulation/presynth/testbench/_primary.dat
74hc373/simulation/presynth/testbench/_primary.dbs
74hc373/simulation/presynth/testbench/_primary.vhd
74hc373/simulation/presynth/_info
74hc373/simulation/presynth/_temp/
74hc373/simulation/presynth/_vmake
74hc373/simulation/run.do
74hc373/simulation/vsim.wlf
74hc373/smartgen/
74hc373/smartgen/smartgen.aws
74hc373/stimulus/
74hc373/stimulus/testbench.v
74hc373/synthesis/
74hc373/synthesis/backup/
74hc373/synthesis/backup/latch8.srr
74hc373/synthesis/coreip/
74hc373/synthesis/latch8.areasrr
74hc373/synthesis/latch8.edn
74hc373/synthesis/latch8.fse
74hc373/synthesis/latch8.htm
74hc373/synthesis/latch8.map
74hc373/synthesis/latch8.pdc
74hc373/synthesis/latch8.sap
74hc373/synthesis/latch8.sdf
74hc373/synthesis/latch8.so
74hc373/synthesis/latch8.srd
74hc373/synthesis/latch8.srm
74hc373/synthesis/latch8.srr
74hc373/synthesis/latch8.srs
74hc373/synthesis/latch8.szr
74hc373/synthesis/latch8.tlg
74hc373/synthesis/latch8_sdc.sdc
74hc373/synthesis/latch8_syn.prd
74hc373/synthesis/latch8_syn.prj
74hc373/synthesis/latch8_syn.sdc
74hc373/synthesis/run_options.txt
74hc373/synthesis/stdout.log
74hc373/synthesis/syntmp/
74hc373/synthesis/syntmp/latch8.plg
74hc373/synthesis/syntmp/latch8_flink.htm
74hc373/synthesis/syntmp/latch8_srr.htm
74hc373/synthesis/syntmp/latch8_toc.htm
74hc373/synthesis/syntmp/sap.log
74hc373/viewdraw/
74hc373/viewdraw/sch/
74hc373/viewdraw/sym/
74hc373/viewdraw/vf/
74hc373/viewdraw/vf/project.lst
74hc373/viewdraw/viewdraw.ini
74hc373/viewdraw/wir/
74hc373/
74hc373/74hc373.prj
74hc373/component/
74hc373/constraint/
74hc373/coreconsole/
74hc373/designer/
74hc373/designer/impl1/
74hc373/designer/impl1/designer.log
74hc373/designer/impl1/latch8.adb
74hc373/designer/impl1/latch8.dtf/
74hc373/designer/impl1/latch8.dtf/verify.log
74hc373/designer/impl1/latch8.ide_des
74hc373/designer/impl1/latch8.pdb
74hc373/designer/impl1/latch8.pdb.depends
74hc373/designer/impl1/latch8.tcl
74hc373/designer/impl1/latch8_fp/
74hc373/designer/impl1/latch8_fp/$$FlashPro_07294.L$$
74hc373/designer/impl1/latch8_fp/latch8.log
74hc373/designer/impl1/latch8_fp/latch8.pro
74hc373/designer/impl1/latch8_fp/projectData/
74hc373/designer/impl1/latch8_fp/projectData/latch8.pdb
74hc373/designer/impl1/simulation/
74hc373/hdl/
74hc373/hdl/74hc373.v
74hc373/phy_synthesis/
74hc373/simulation/
74hc373/simulation/modelsim.ini
74hc373/simulation/modelsim.ini.sav
74hc373/simulation/modelsim.log
74hc373/simulation/presynth/
74hc373/simulation/presynth/latch8/
74hc373/simulation/presynth/latch8/verilog.psm
74hc373/simulation/presynth/latch8/_primary.dat
74hc373/simulation/presynth/latch8/_primary.dbs
74hc373/simulation/presynth/latch8/_primary.vhd
74hc373/simulation/presynth/testbench/
74hc373/simulation/presynth/testbench/verilog.psm
74hc373/simulation/presynth/testbench/_primary.dat
74hc373/simulation/presynth/testbench/_primary.dbs
74hc373/simulation/presynth/testbench/_primary.vhd
74hc373/simulation/presynth/_info
74hc373/simulation/presynth/_temp/
74hc373/simulation/presynth/_vmake
74hc373/simulation/run.do
74hc373/simulation/vsim.wlf
74hc373/smartgen/
74hc373/smartgen/smartgen.aws
74hc373/stimulus/
74hc373/stimulus/testbench.v
74hc373/synthesis/
74hc373/synthesis/backup/
74hc373/synthesis/backup/latch8.srr
74hc373/synthesis/coreip/
74hc373/synthesis/latch8.areasrr
74hc373/synthesis/latch8.edn
74hc373/synthesis/latch8.fse
74hc373/synthesis/latch8.htm
74hc373/synthesis/latch8.map
74hc373/synthesis/latch8.pdc
74hc373/synthesis/latch8.sap
74hc373/synthesis/latch8.sdf
74hc373/synthesis/latch8.so
74hc373/synthesis/latch8.srd
74hc373/synthesis/latch8.srm
74hc373/synthesis/latch8.srr
74hc373/synthesis/latch8.srs
74hc373/synthesis/latch8.szr
74hc373/synthesis/latch8.tlg
74hc373/synthesis/latch8_sdc.sdc
74hc373/synthesis/latch8_syn.prd
74hc373/synthesis/latch8_syn.prj
74hc373/synthesis/latch8_syn.sdc
74hc373/synthesis/run_options.txt
74hc373/synthesis/stdout.log
74hc373/synthesis/syntmp/
74hc373/synthesis/syntmp/latch8.plg
74hc373/synthesis/syntmp/latch8_flink.htm
74hc373/synthesis/syntmp/latch8_srr.htm
74hc373/synthesis/syntmp/latch8_toc.htm
74hc373/synthesis/syntmp/sap.log
74hc373/viewdraw/
74hc373/viewdraw/sch/
74hc373/viewdraw/sym/
74hc373/viewdraw/vf/
74hc373/viewdraw/vf/project.lst
74hc373/viewdraw/viewdraw.ini
74hc373/viewdraw/wir/
1999-2046 搜珍网 All Rights Reserved.
本站作为网络服务提供者,仅为网络服务对象提供信息存储空间,仅对用户上载内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。
