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文件名称:Xil3SD1800A_MIG_simplifiedUI_vlog_v92
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verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
相关搜索： ddr2
DDR2 verilog
dsp verilog
Verilog DDR2
Verilog DSP
lm75 verilog .v
ddr2 source verilog
spartan ddr
VHDL DSP
verilog
(系统自动生成,下载前可以参看下载内容)
下载文件列表
avnet_notice_2008.txt
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/datasheet.txt
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/ddr2_32mx32.bit
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/log.txt
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/mig.prj
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/create_ise.bat
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/ddr2_32Mx32.cdc
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/ddr2_32Mx32.ucf
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/ddr2_32Mx32_user_interface.cpj
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/ddr2_speedway.bat
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/ddr2_speedway.ise
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/ddr2_speedway.ise_ISE_Backup
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/ise_flow.bat
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/ise_run.txt
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/readme.txt
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/set_ise_prop.txt
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_addr_gen_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_cal_ctl_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_cal_top.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_clk_dcm.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_cmd_fsm_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_cmp_data_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_controller_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_controller_iobs_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_data_counter_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_data_path_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_data_path_iobs_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_data_read_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_data_read_controller_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_data_write_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_dqs_delay.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_fifo_0_wr_en_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_fifo_1_wr_en_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_infrastructure.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_infrastructure_iobs_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_infrastructure_top_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_iobs_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_main_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_parameters_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_ram8d_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_rd_gray_cntr.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_s3_dm_iob_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_s3_dqs_iob.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_s3_dq_iob.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_tap_dly.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_top_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_user_logic_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_wr_gray_cntr.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/sim/
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/sim/ddr2_model.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/sim/ddr2_model_parameters.vh
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/sim/glbl.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/sim/sim.do
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/sim/sim.exe
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/sim/simulation_help.chm
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/sim/sim_tb_top.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/synth/
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/synth/ddr2_32Mx32.lso
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/synth/ddr2_32Mx32.prj
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/synth/ddr2_32Mx32.sdc
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/synth/mem_interface_top.xcf
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/synth/mem_interface_top_synp.sdc
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/synth/script_synp.tcl
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/
Xil3SD1800A_MIG_simplifiedUI_vlog_v92.pdf
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/datasheet.txt
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/ddr2_32mx32.bit
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/log.txt
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/mig.prj
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/create_ise.bat
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/ddr2_32Mx32.cdc
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/ddr2_32Mx32.ucf
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/ddr2_32Mx32_user_interface.cpj
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/ddr2_speedway.bat
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/ddr2_speedway.ise
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/ddr2_speedway.ise_ISE_Backup
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/ise_flow.bat
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/ise_run.txt
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/readme.txt
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/par/set_ise_prop.txt
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_addr_gen_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_cal_ctl_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_cal_top.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_clk_dcm.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_cmd_fsm_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_cmp_data_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_controller_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_controller_iobs_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_data_counter_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_data_path_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_data_path_iobs_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_data_read_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_data_read_controller_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_data_write_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_dqs_delay.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_fifo_0_wr_en_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_fifo_1_wr_en_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_infrastructure.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_infrastructure_iobs_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_infrastructure_top_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_iobs_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_main_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_parameters_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_ram8d_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_rd_gray_cntr.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_s3_dm_iob_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_s3_dqs_iob.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_s3_dq_iob.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_tap_dly.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_top_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_user_logic_0.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/rtl/ddr2_32Mx32_wr_gray_cntr.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/sim/
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/sim/ddr2_model.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/sim/ddr2_model_parameters.vh
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/sim/glbl.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/sim/sim.do
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/sim/sim.exe
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/sim/simulation_help.chm
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/sim/sim_tb_top.v
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/synth/
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/synth/ddr2_32Mx32.lso
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/synth/ddr2_32Mx32.prj
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/synth/ddr2_32Mx32.sdc
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/synth/mem_interface_top.xcf
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/synth/mem_interface_top_synp.sdc
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/synth/script_synp.tcl
Xil3SD1800A_MIG_simplifiedUI_vlog_v92/
Xil3SD1800A_MIG_simplifiedUI_vlog_v92.pdf
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