文件名称:spi_latest.tar
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- 上传时间:2012-11-16
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文件大小:2.5mb
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用verilog HDL编写的SPI控制器,从国外网站上找到的。-SPI (Serial Peripheral Interface) is serial, synchronous, full duplex communication protocol. It is widely used as a board-level interface between different devices such as microcontrollers, DACs, ADCs and others.
相关搜索: spi
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下载文件列表
./
./spi/
./spi/tags/
./spi/tags/rel_2/
./spi/tags/rel_2/bench/
./spi/tags/rel_2/bench/verilog/
./spi/tags/rel_2/bench/verilog/wb_master_model.v
./spi/tags/rel_2/bench/verilog/tb_spi_top.v
./spi/tags/rel_2/bench/verilog/spi_slave_model.v
./spi/tags/rel_2/doc/
./spi/tags/rel_2/doc/src/
./spi/tags/rel_2/doc/src/spi.doc
./spi/tags/rel_2/doc/spi.pdf
./spi/tags/rel_2/rtl/
./spi/tags/rel_2/rtl/verilog/
./spi/tags/rel_2/rtl/verilog/spi_clgen.v
./spi/tags/rel_2/rtl/verilog/timescale.v
./spi/tags/rel_2/rtl/verilog/spi_defines.v
./spi/tags/rel_2/rtl/verilog/spi_shift.v
./spi/tags/rel_2/rtl/verilog/spi_top.v
./spi/tags/rel_2/sim/
./spi/tags/rel_2/sim/run/
./spi/tags/rel_2/sim/run/sim
./spi/tags/rel_2/sim/run/tcl.scr
./spi/tags/initial/
./spi/tags/initial/bench/
./spi/tags/initial/bench/verilog/
./spi/tags/initial/bench/verilog/wb_master_model.v
./spi/tags/initial/bench/verilog/tb_spi_top.v
./spi/tags/initial/bench/verilog/spi_slave_model.v
./spi/tags/initial/doc/
./spi/tags/initial/doc/src/
./spi/tags/initial/doc/src/spi.doc
./spi/tags/initial/rtl/
./spi/tags/initial/rtl/verilog/
./spi/tags/initial/rtl/verilog/spi_clgen.v
./spi/tags/initial/rtl/verilog/timescale.v
./spi/tags/initial/rtl/verilog/spi_defines.v
./spi/tags/initial/rtl/verilog/spi_shift.v
./spi/tags/initial/rtl/verilog/spi_top.v
./spi/tags/initial/sim/
./spi/tags/initial/sim/run/
./spi/tags/initial/sim/run/sim
./spi/tags/initial/sim/run/tcl.scr
./spi/tags/rel_1/
./spi/tags/rel_1/bench/
./spi/tags/rel_1/bench/verilog/
./spi/tags/rel_1/bench/verilog/wb_master_model.v
./spi/tags/rel_1/bench/verilog/tb_spi_top.v
./spi/tags/rel_1/bench/verilog/spi_slave_model.v
./spi/tags/rel_1/doc/
./spi/tags/rel_1/doc/src/
./spi/tags/rel_1/doc/src/spi.doc
./spi/tags/rel_1/doc/spi.pdf
./spi/tags/rel_1/rtl/
./spi/tags/rel_1/rtl/verilog/
./spi/tags/rel_1/rtl/verilog/spi_clgen.v
./spi/tags/rel_1/rtl/verilog/timescale.v
./spi/tags/rel_1/rtl/verilog/spi_defines.v
./spi/tags/rel_1/rtl/verilog/spi_shift.v
./spi/tags/rel_1/rtl/verilog/spi_top.v
./spi/tags/rel_1/sim/
./spi/tags/rel_1/sim/run/
./spi/tags/rel_1/sim/run/sim
./spi/tags/rel_1/sim/run/tcl.scr
./spi/tags/rel_7/
./spi/tags/rel_7/bench/
./spi/tags/rel_7/bench/verilog/
./spi/tags/rel_7/bench/verilog/wb_master_model.v
./spi/tags/rel_7/bench/verilog/tb_spi_top.v
./spi/tags/rel_7/bench/verilog/spi_slave_model.v
./spi/tags/rel_7/doc/
./spi/tags/rel_7/doc/src/
./spi/tags/rel_7/doc/src/spi.doc
./spi/tags/rel_7/doc/spi.pdf
./spi/tags/rel_7/rtl/
./spi/tags/rel_7/rtl/verilog/
./spi/tags/rel_7/rtl/verilog/spi_clgen.v
./spi/tags/rel_7/rtl/verilog/timescale.v
./spi/tags/rel_7/rtl/verilog/spi_defines.v
./spi/tags/rel_7/rtl/verilog/spi_shift.v
./spi/tags/rel_7/rtl/verilog/spi_top.v
./spi/tags/rel_7/sim/
./spi/tags/rel_7/sim/run/
./spi/tags/rel_7/sim/run/sim
./spi/tags/rel_7/sim/run/tcl.scr
./spi/tags/rel_8/
./spi/tags/rel_8/bench/
./spi/tags/rel_8/bench/verilog/
./spi/tags/rel_8/bench/verilog/wb_master_model.v
./spi/tags/rel_8/bench/verilog/tb_spi_top.v
./spi/tags/rel_8/bench/verilog/spi_slave_model.v
./spi/tags/rel_8/doc/
./spi/tags/rel_8/doc/src/
./spi/tags/rel_8/doc/src/spi.doc
./spi/tags/rel_8/doc/spi.pdf
./spi/tags/rel_8/rtl/
./spi/tags/rel_8/rtl/verilog/
./spi/tags/rel_8/rtl/verilog/spi_clgen.v
./spi/tags/rel_8/rtl/verilog/timescale.v
./spi/tags/rel_8/rtl/verilog/spi_defines.v
./spi/tags/rel_8/rtl/verilog/spi_shift.v
./spi/tags/rel_8/rtl/verilog/spi_top.v
./spi/tags/rel_8/sim/
./spi/tags/rel_8/sim/rtl_sim/
./spi/tags/rel_8/sim/rtl_sim/run/
./spi/tags/rel_8/sim/rtl_sim/run/run_sim
./spi/tags/rel_8/sim/rtl_sim/run/sim.fl
./spi/tags/rel_8/sim/rtl_sim/run/rtl.fl
./spi/tags/rel_5/
./spi/tags/rel_5/bench/
./spi/tags/rel_5/bench/verilog/
./spi/tags/rel_5/bench/verilog/wb_master_model.v
./spi/tags/rel_5/bench/verilog/tb_spi_top.v
./spi/tags/rel_5/bench/verilog/spi_slave_model.v
./spi/tags/rel_5/doc/
./spi/tags/rel_5/doc/src/
./spi/tags/rel_5/doc/src/spi.doc
./spi/tags/rel_5/doc/spi.pdf
./spi/tags/rel_5/rtl/
./spi/tags/rel_5/rtl/verilog/
./spi/tags/rel_5/rtl/verilog/spi_clgen.v
./spi/tags/rel_5/rtl/verilog/timescale.v
./spi/tags/rel_5/rtl/verilog/spi_defines.v
./spi/tags/rel_5/rtl/verilog/spi_shift.v
./spi/tags/rel_5/rtl/verilog/spi_top.v
./spi/tags/rel_5/sim/
./spi/tags/rel_5/sim/run/
./spi/tags/rel_5/sim/run/sim
./spi/tags/rel_5/sim/run/tcl.scr
./spi/tags/rel_6/
./spi/tags/rel_6/bench/
./spi/tags/rel_6/bench/verilog/
./spi/tags/rel_6/bench/verilog/wb_master_model.v
./spi/tags/rel_6/bench/verilog/tb_spi_top.v
./spi/tags/rel_6/bench/verilog/spi_slave_model.v
./spi/tags/rel_6/doc/
./spi/tags/rel_6/doc/src/
./spi/tags/rel_6/doc/src/spi.doc
./spi/tags/rel_6/doc/spi.pdf
./spi/tags/rel_6/rtl/
./spi/tags/rel_6/rtl/verilog/
./spi/tags/rel_6/rtl/verilog/spi_clgen.v
./spi/tags/rel_6/rtl/verilog/timescale.v
./spi/tags/rel_6/rtl/verilog/spi_defines.v
./spi/tags/rel_6/rtl/verilog/spi_shift.v
./spi/tags/rel_6/rtl/verilog/spi_top.v
./spi/tags/rel_6/sim/
./spi/tags/rel_6/sim/run/
./spi/tags/rel_6/sim/run/sim
./spi/tags/rel_6/sim/run/tcl.scr
./spi/tags/rel_3/
./spi/tags/rel_3/bench/
./spi/tags/rel_3/bench/verilog/
./spi/tags/rel_3/bench/verilog/wb_master_model.v
./spi/tags/rel_3
./spi/
./spi/tags/
./spi/tags/rel_2/
./spi/tags/rel_2/bench/
./spi/tags/rel_2/bench/verilog/
./spi/tags/rel_2/bench/verilog/wb_master_model.v
./spi/tags/rel_2/bench/verilog/tb_spi_top.v
./spi/tags/rel_2/bench/verilog/spi_slave_model.v
./spi/tags/rel_2/doc/
./spi/tags/rel_2/doc/src/
./spi/tags/rel_2/doc/src/spi.doc
./spi/tags/rel_2/doc/spi.pdf
./spi/tags/rel_2/rtl/
./spi/tags/rel_2/rtl/verilog/
./spi/tags/rel_2/rtl/verilog/spi_clgen.v
./spi/tags/rel_2/rtl/verilog/timescale.v
./spi/tags/rel_2/rtl/verilog/spi_defines.v
./spi/tags/rel_2/rtl/verilog/spi_shift.v
./spi/tags/rel_2/rtl/verilog/spi_top.v
./spi/tags/rel_2/sim/
./spi/tags/rel_2/sim/run/
./spi/tags/rel_2/sim/run/sim
./spi/tags/rel_2/sim/run/tcl.scr
./spi/tags/initial/
./spi/tags/initial/bench/
./spi/tags/initial/bench/verilog/
./spi/tags/initial/bench/verilog/wb_master_model.v
./spi/tags/initial/bench/verilog/tb_spi_top.v
./spi/tags/initial/bench/verilog/spi_slave_model.v
./spi/tags/initial/doc/
./spi/tags/initial/doc/src/
./spi/tags/initial/doc/src/spi.doc
./spi/tags/initial/rtl/
./spi/tags/initial/rtl/verilog/
./spi/tags/initial/rtl/verilog/spi_clgen.v
./spi/tags/initial/rtl/verilog/timescale.v
./spi/tags/initial/rtl/verilog/spi_defines.v
./spi/tags/initial/rtl/verilog/spi_shift.v
./spi/tags/initial/rtl/verilog/spi_top.v
./spi/tags/initial/sim/
./spi/tags/initial/sim/run/
./spi/tags/initial/sim/run/sim
./spi/tags/initial/sim/run/tcl.scr
./spi/tags/rel_1/
./spi/tags/rel_1/bench/
./spi/tags/rel_1/bench/verilog/
./spi/tags/rel_1/bench/verilog/wb_master_model.v
./spi/tags/rel_1/bench/verilog/tb_spi_top.v
./spi/tags/rel_1/bench/verilog/spi_slave_model.v
./spi/tags/rel_1/doc/
./spi/tags/rel_1/doc/src/
./spi/tags/rel_1/doc/src/spi.doc
./spi/tags/rel_1/doc/spi.pdf
./spi/tags/rel_1/rtl/
./spi/tags/rel_1/rtl/verilog/
./spi/tags/rel_1/rtl/verilog/spi_clgen.v
./spi/tags/rel_1/rtl/verilog/timescale.v
./spi/tags/rel_1/rtl/verilog/spi_defines.v
./spi/tags/rel_1/rtl/verilog/spi_shift.v
./spi/tags/rel_1/rtl/verilog/spi_top.v
./spi/tags/rel_1/sim/
./spi/tags/rel_1/sim/run/
./spi/tags/rel_1/sim/run/sim
./spi/tags/rel_1/sim/run/tcl.scr
./spi/tags/rel_7/
./spi/tags/rel_7/bench/
./spi/tags/rel_7/bench/verilog/
./spi/tags/rel_7/bench/verilog/wb_master_model.v
./spi/tags/rel_7/bench/verilog/tb_spi_top.v
./spi/tags/rel_7/bench/verilog/spi_slave_model.v
./spi/tags/rel_7/doc/
./spi/tags/rel_7/doc/src/
./spi/tags/rel_7/doc/src/spi.doc
./spi/tags/rel_7/doc/spi.pdf
./spi/tags/rel_7/rtl/
./spi/tags/rel_7/rtl/verilog/
./spi/tags/rel_7/rtl/verilog/spi_clgen.v
./spi/tags/rel_7/rtl/verilog/timescale.v
./spi/tags/rel_7/rtl/verilog/spi_defines.v
./spi/tags/rel_7/rtl/verilog/spi_shift.v
./spi/tags/rel_7/rtl/verilog/spi_top.v
./spi/tags/rel_7/sim/
./spi/tags/rel_7/sim/run/
./spi/tags/rel_7/sim/run/sim
./spi/tags/rel_7/sim/run/tcl.scr
./spi/tags/rel_8/
./spi/tags/rel_8/bench/
./spi/tags/rel_8/bench/verilog/
./spi/tags/rel_8/bench/verilog/wb_master_model.v
./spi/tags/rel_8/bench/verilog/tb_spi_top.v
./spi/tags/rel_8/bench/verilog/spi_slave_model.v
./spi/tags/rel_8/doc/
./spi/tags/rel_8/doc/src/
./spi/tags/rel_8/doc/src/spi.doc
./spi/tags/rel_8/doc/spi.pdf
./spi/tags/rel_8/rtl/
./spi/tags/rel_8/rtl/verilog/
./spi/tags/rel_8/rtl/verilog/spi_clgen.v
./spi/tags/rel_8/rtl/verilog/timescale.v
./spi/tags/rel_8/rtl/verilog/spi_defines.v
./spi/tags/rel_8/rtl/verilog/spi_shift.v
./spi/tags/rel_8/rtl/verilog/spi_top.v
./spi/tags/rel_8/sim/
./spi/tags/rel_8/sim/rtl_sim/
./spi/tags/rel_8/sim/rtl_sim/run/
./spi/tags/rel_8/sim/rtl_sim/run/run_sim
./spi/tags/rel_8/sim/rtl_sim/run/sim.fl
./spi/tags/rel_8/sim/rtl_sim/run/rtl.fl
./spi/tags/rel_5/
./spi/tags/rel_5/bench/
./spi/tags/rel_5/bench/verilog/
./spi/tags/rel_5/bench/verilog/wb_master_model.v
./spi/tags/rel_5/bench/verilog/tb_spi_top.v
./spi/tags/rel_5/bench/verilog/spi_slave_model.v
./spi/tags/rel_5/doc/
./spi/tags/rel_5/doc/src/
./spi/tags/rel_5/doc/src/spi.doc
./spi/tags/rel_5/doc/spi.pdf
./spi/tags/rel_5/rtl/
./spi/tags/rel_5/rtl/verilog/
./spi/tags/rel_5/rtl/verilog/spi_clgen.v
./spi/tags/rel_5/rtl/verilog/timescale.v
./spi/tags/rel_5/rtl/verilog/spi_defines.v
./spi/tags/rel_5/rtl/verilog/spi_shift.v
./spi/tags/rel_5/rtl/verilog/spi_top.v
./spi/tags/rel_5/sim/
./spi/tags/rel_5/sim/run/
./spi/tags/rel_5/sim/run/sim
./spi/tags/rel_5/sim/run/tcl.scr
./spi/tags/rel_6/
./spi/tags/rel_6/bench/
./spi/tags/rel_6/bench/verilog/
./spi/tags/rel_6/bench/verilog/wb_master_model.v
./spi/tags/rel_6/bench/verilog/tb_spi_top.v
./spi/tags/rel_6/bench/verilog/spi_slave_model.v
./spi/tags/rel_6/doc/
./spi/tags/rel_6/doc/src/
./spi/tags/rel_6/doc/src/spi.doc
./spi/tags/rel_6/doc/spi.pdf
./spi/tags/rel_6/rtl/
./spi/tags/rel_6/rtl/verilog/
./spi/tags/rel_6/rtl/verilog/spi_clgen.v
./spi/tags/rel_6/rtl/verilog/timescale.v
./spi/tags/rel_6/rtl/verilog/spi_defines.v
./spi/tags/rel_6/rtl/verilog/spi_shift.v
./spi/tags/rel_6/rtl/verilog/spi_top.v
./spi/tags/rel_6/sim/
./spi/tags/rel_6/sim/run/
./spi/tags/rel_6/sim/run/sim
./spi/tags/rel_6/sim/run/tcl.scr
./spi/tags/rel_3/
./spi/tags/rel_3/bench/
./spi/tags/rel_3/bench/verilog/
./spi/tags/rel_3/bench/verilog/wb_master_model.v
./spi/tags/rel_3
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