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文件名称:lab1

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
  • 上传时间：
    2012-11-16
  • 文件大小：
    422.03kb
  • 已下载：
    0次
  • 提 供 者：
    n*****
  • 相关连接：
    无
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下载文件列表

lab1/4add/
lab1/4add/adder4bit.asm.rpt
lab1/4add/adder4bit.done
lab1/4add/adder4bit.fit.rpt
lab1/4add/adder4bit.fit.summary
lab1/4add/adder4bit.flow.rpt
lab1/4add/adder4bit.map.rpt
lab1/4add/adder4bit.map.summary
lab1/4add/adder4bit.merge.rpt
lab1/4add/adder4bit.pin
lab1/4add/adder4bit.pof
lab1/4add/adder4bit.qpf
lab1/4add/adder4bit.qsf
lab1/4add/adder4bit.qws
lab1/4add/adder4bit.sof
lab1/4add/adder4bit.tan.rpt
lab1/4add/adder4bit.tan.summary
lab1/4add/adder4bit.vhd
lab1/4add/db/
lab1/4add/db/adder4bit.(0).cnf.cdb
lab1/4add/db/adder4bit.(0).cnf.hdb
lab1/4add/db/adder4bit.(1).cnf.cdb
lab1/4add/db/adder4bit.(1).cnf.hdb
lab1/4add/db/adder4bit.(2).cnf.cdb
lab1/4add/db/adder4bit.(2).cnf.hdb
lab1/4add/db/adder4bit.asm.qmsg
lab1/4add/db/adder4bit.cbx.xml
lab1/4add/db/adder4bit.cmp.bpm
lab1/4add/db/adder4bit.cmp.cdb
lab1/4add/db/adder4bit.cmp.ecobp
lab1/4add/db/adder4bit.cmp.hdb
lab1/4add/db/adder4bit.cmp.logdb
lab1/4add/db/adder4bit.cmp.rdb
lab1/4add/db/adder4bit.cmp.tdb
lab1/4add/db/adder4bit.cmp0.ddb
lab1/4add/db/adder4bit.cmp_bb.cdb
lab1/4add/db/adder4bit.cmp_bb.hdb
lab1/4add/db/adder4bit.cmp_bb.logdb
lab1/4add/db/adder4bit.cmp_bb.rcf
lab1/4add/db/adder4bit.dbp
lab1/4add/db/adder4bit.db_info
lab1/4add/db/adder4bit.eco.cdb
lab1/4add/db/adder4bit.fit.qmsg
lab1/4add/db/adder4bit.hier_info
lab1/4add/db/adder4bit.hif
lab1/4add/db/adder4bit.map.bpm
lab1/4add/db/adder4bit.map.cdb
lab1/4add/db/adder4bit.map.ecobp
lab1/4add/db/adder4bit.map.hdb
lab1/4add/db/adder4bit.map.logdb
lab1/4add/db/adder4bit.map.qmsg
lab1/4add/db/adder4bit.map_bb.cdb
lab1/4add/db/adder4bit.map_bb.hdb
lab1/4add/db/adder4bit.map_bb.logdb
lab1/4add/db/adder4bit.merge.qmsg
lab1/4add/db/adder4bit.pre_map.cdb
lab1/4add/db/adder4bit.pre_map.hdb
lab1/4add/db/adder4bit.psp
lab1/4add/db/adder4bit.pss
lab1/4add/db/adder4bit.rtlv.hdb
lab1/4add/db/adder4bit.rtlv_sg.cdb
lab1/4add/db/adder4bit.rtlv_sg_swap.cdb
lab1/4add/db/adder4bit.sgdiff.cdb
lab1/4add/db/adder4bit.sgdiff.hdb
lab1/4add/db/adder4bit.sld_design_entry.sci
lab1/4add/db/adder4bit.sld_design_entry_dsc.sci
lab1/4add/db/adder4bit.syn_hier_info
lab1/4add/db/adder4bit.tan.qmsg
lab1/Fadd_portmap/
lab1/Fadd_portmap/db/
lab1/Fadd_portmap/db/f_add_pm.(0).cnf.cdb
lab1/Fadd_portmap/db/f_add_pm.(0).cnf.hdb
lab1/Fadd_portmap/db/f_add_pm.(1).cnf.cdb
lab1/Fadd_portmap/db/f_add_pm.(1).cnf.hdb
lab1/Fadd_portmap/db/f_add_pm.asm.qmsg
lab1/Fadd_portmap/db/f_add_pm.cbx.xml
lab1/Fadd_portmap/db/f_add_pm.cmp.bpm
lab1/Fadd_portmap/db/f_add_pm.cmp.cdb
lab1/Fadd_portmap/db/f_add_pm.cmp.ecobp
lab1/Fadd_portmap/db/f_add_pm.cmp.hdb
lab1/Fadd_portmap/db/f_add_pm.cmp.logdb
lab1/Fadd_portmap/db/f_add_pm.cmp.rdb
lab1/Fadd_portmap/db/f_add_pm.cmp.tdb
lab1/Fadd_portmap/db/f_add_pm.cmp0.ddb
lab1/Fadd_portmap/db/f_add_pm.cmp_bb.cdb
lab1/Fadd_portmap/db/f_add_pm.cmp_bb.hdb
lab1/Fadd_portmap/db/f_add_pm.cmp_bb.logdb
lab1/Fadd_portmap/db/f_add_pm.cmp_bb.rcf
lab1/Fadd_portmap/db/f_add_pm.dbp
lab1/Fadd_portmap/db/f_add_pm.db_info
lab1/Fadd_portmap/db/f_add_pm.eco.cdb
lab1/Fadd_portmap/db/f_add_pm.eds_overflow
lab1/Fadd_portmap/db/f_add_pm.fit.qmsg
lab1/Fadd_portmap/db/f_add_pm.fnsim.cdb
lab1/Fadd_portmap/db/f_add_pm.fnsim.hdb
lab1/Fadd_portmap/db/f_add_pm.fnsim.qmsg
lab1/Fadd_portmap/db/f_add_pm.hier_info
lab1/Fadd_portmap/db/f_add_pm.hif
lab1/Fadd_portmap/db/f_add_pm.map.bpm
lab1/Fadd_portmap/db/f_add_pm.map.cdb
lab1/Fadd_portmap/db/f_add_pm.map.ecobp
lab1/Fadd_portmap/db/f_add_pm.map.hdb
lab1/Fadd_portmap/db/f_add_pm.map.logdb
lab1/Fadd_portmap/db/f_add_pm.map.qmsg
lab1/Fadd_portmap/db/f_add_pm.map_bb.cdb
lab1/Fadd_portmap/db/f_add_pm.map_bb.hdb
lab1/Fadd_portmap/db/f_add_pm.map_bb.logdb
lab1/Fadd_portmap/db/f_add_pm.merge.qmsg
lab1/Fadd_portmap/db/f_add_pm.pre_map.cdb
lab1/Fadd_portmap/db/f_add_pm.pre_map.hdb
lab1/Fadd_portmap/db/f_add_pm.psp
lab1/Fadd_portmap/db/f_add_pm.pss
lab1/Fadd_portmap/db/f_add_pm.rtlv.hdb
lab1/Fadd_portmap/db/f_add_pm.rtlv_sg.cdb
lab1/Fadd_portmap/db/f_add_pm.rtlv_sg_swap.cdb
lab1/Fadd_portmap/db/f_add_pm.sgdiff.cdb
lab1/Fadd_portmap/db/f_add_pm.sgdiff.hdb
lab1/Fadd_portmap/db/f_add_pm.sim.hdb
lab1/Fadd_portmap/db/f_add_pm.sim.qmsg
lab1/Fadd_portmap/db/f_add_pm.sim.rdb
lab1/Fadd_portmap/db/f_add_pm.sim_ori.vwf
lab1/Fadd_portmap/db/f_add_pm.sld_design_entry.sci
lab1/Fadd_portmap/db/f_add_pm.sld_design_entry_dsc.sci
lab1/Fadd_portmap/db/f_add_pm.syn_hier_info
lab1/Fadd_portmap/db/f_add_pm.tan.qmsg
lab1/Fadd_portmap/db/wed.wsf
lab1/Fadd_portmap/f_add_pm.asm.rpt
lab1/Fadd_portmap/f_add_pm.done
lab1/Fadd_portmap/f_add_pm.fit.rpt
lab1/Fadd_portmap/f_add_pm.fit.summary
lab1/Fadd_portmap/f_add_pm.flow.rpt
lab1/Fadd_portmap/f_add_pm.map.rpt
lab1/Fadd_portmap/f_add_pm.map.summary
lab1/Fadd_portmap/f_add_pm.merge.rpt
lab1/Fadd_portmap/f_add_pm.pin
lab1/Fadd_portmap/f_add_pm.pof
lab1/Fadd_portmap/f_add_pm.qpf
lab1/Fadd_portmap/f_add_pm.qsf
lab1/Fadd_portmap/f_add_pm.qws
lab1/Fadd_portmap/f_add_pm.sim.rpt
lab1/Fadd_portmap/f_add_pm.sof
lab1/Fadd_portmap/f_add_pm.tan.rpt
lab1/Fadd_portmap/f_add_pm.tan.summary
lab1/Fadd_portmap/f_add_pm.vhd
lab1/Fadd_portmap/f_add_pm.vwf
lab1/hadd/
lab1/hadd/db/
lab1/hadd/db/h_add.(0).cnf.cdb
lab1/hadd/db/h_a

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