HW5_Source/alu.vhd
HW5_Source/brcond.vhd
HW5_Source/control.vhd
HW5_Source/ext.vhd
HW5_Source/forward.vhd
HW5_Source/mem_Interface.vhd
HW5_Source/myrisc_pipeline_realMem.vhd
HW5_Source/myrisc_pipeline_real_top.ucf
HW5_Source/myrisc_pipeline_top.vhd
HW5_Source/myrisc_pkg.vhd
HW5_Source/phase_gen.vhd
HW5_Source/reg.vhd
HW5_Source/regfile.vhd
HW5_Source/shifter.vhd
HW5_Source/shl8.vhd
HW5_Source/converted/memory_real.v
HW5_Source/converted/myrisc_pkg.v
HW5_Source/converted/tb_myrisc_pipe_realMem.v
HW5_Source/converted/transcript
HW5_Source/hint/myrisc_pipeline_realMem.v
HW5_Source/hint/reg16.v
HW5_Source/simulation/data.txt
HW5_Source/simulation/memory_real.vhd
HW5_Source/simulation/mycmd_final.txt
HW5_Source/simulation/tb_myrisc_pipeline_realMem.vhd
HW5/alu.v
HW5/brcond.v
HW5/control.v
HW5/data.txt
HW5/forward.v
HW5/HW5.cr.mti
HW5/HW5.mpf
HW5/HW5_report.hwp
HW5/immext.v
HW5/memory_real.v
HW5/mem_Interface.v
HW5/mycmd_final.txt
HW5/myrisc_pipeline_realMem.v
HW5/myrisc_pipeline_top.v
HW5/myrisc_pkg.txt
HW5/phase_gen.v
HW5/reg16.v
HW5/regfile.v
HW5/shifter.v
HW5/shl8.v
HW5/tb_myrisc_pipe_realMem.v
HW5/transcript
HW5/vsim.wlf
HW5/wave.do
HW5/work/_info
HW5/work/alu/verilog.asm
HW5/work/alu/_primary.dat
HW5/work/alu/_primary.vhd
HW5/work/brcond/verilog.asm
HW5/work/brcond/_primary.dat
HW5/work/brcond/_primary.vhd
HW5/work/forward/verilog.asm
HW5/work/forward/_primary.dat
HW5/work/forward/_primary.vhd
HW5/work/immext/verilog.asm
HW5/work/immext/_primary.dat
HW5/work/immext/_primary.vhd
HW5/work/instr_decoder/verilog.asm
HW5/work/instr_decoder/_primary.dat
HW5/work/instr_decoder/_primary.vhd
HW5/work/meminterface_8_16/verilog.asm
HW5/work/meminterface_8_16/_primary.dat
HW5/work/meminterface_8_16/_primary.vhd
HW5/work/memory/verilog.asm
HW5/work/memory/_primary.dat
HW5/work/memory/_primary.vhd
HW5/work/myrisc_pipeline_4ph/verilog.asm
HW5/work/myrisc_pipeline_4ph/_primary.dat
HW5/work/myrisc_pipeline_4ph/_primary.vhd
HW5/work/myrisc_pipeline_real_top/verilog.asm
HW5/work/myrisc_pipeline_real_top/_primary.dat
HW5/work/myrisc_pipeline_real_top/_primary.vhd
HW5/work/phase_gen/verilog.asm
HW5/work/phase_gen/_primary.dat
HW5/work/phase_gen/_primary.vhd
HW5/work/reg16/verilog.asm
HW5/work/reg16/_primary.dat
HW5/work/reg16/_primary.vhd
HW5/work/regfile/verilog.asm
HW5/work/regfile/_primary.dat
HW5/work/regfile/_primary.vhd
HW5/work/shifter/verilog.asm
HW5/work/shifter/_primary.dat
HW5/work/shifter/_primary.vhd
HW5/work/shl8/verilog.asm
HW5/work/shl8/_primary.dat
HW5/work/shl8/_primary.vhd
HW5/work/slice/verilog.asm
HW5/work/slice/_primary.dat
HW5/work/slice/_primary.vhd
HW5/work/tb_myrisc_top_real/verilog.asm
HW5/work/tb_myrisc_top_real/_primary.dat
HW5/work/tb_myrisc_top_real/_primary.vhd