搜索资源列表
Booth2_16
- 这是16位booth阶2的有符号乘法器及其相关测试程序-16 bit booth order 2 with symbolic multipliers and related test procedures
ga
- 电路演化，可以生成一个两位乘两位的乘法器-Circuits have evolved to generate a two by two multipliers
parallelmultiplier
- 高速并行乘法器 请认真书写上传资料的详细功能、包含内容说明(至少要20个字)。尽量不要让站长把时间都花费在为您修正说明上。压缩包解压时不能有密码。-parallel multiplier .a parallel multiplier.a parallel multiplier.a parallel multiplier a a a a parallel multiplier a parallel multiplier a parallel multiplier a
MUL
- 4位乘法器用来监测心跳到，与计数器搭配使用-this is 4 multiply to get heart beats
mux16
- 基于DE2-70开发板的十六位乘十六位的乘法器，程序简单易懂-Based on the DE2-70 development board 16 x 16 multiplier, easy to understand
test_128_tp
- 128位乘法器，verilog实现，椭圆加密算法-128 multiplier, verilog achieve, elliptical encryption algorithm
mux_16bit_sign
- 16位有符号和无符号乘法器FPGA源代码-16-bit signed and unsigned multiplier FPGA source code
Multiplier
- 设计一个能进行两个十进制数相乘的乘法器，乘数和被乘数均小于100。-Can design a multiplier multiplying two decimal numbers, the multiplier and multiplicand are less than 100.
Analog-multiplier
- 实现了乘法器功能，包含仿真电路和仿真实现程序-Achieve a multiplier features, including simulation, and circuit simulation program to achieve
RS(204-188)decoder_verilog
- 采用verilog实现的有限域GF(28)弱对偶基乘法器，本原多项式: p(x) = x^8 + x^4 + x^3 + x^2 + 1 ，多项式基: {1, a^1, a^2, a^3, a^4, a^5, a^6, a^7}，弱对偶基: {1+a^2, a^1, 1, a^7, a^6, a^5, a^4, a^3+a^7}-Verilog achieved using the finite field GF (28) weak dual basis multiplier
15x15mul
- 自己写的布斯4算法的华莱士树无符号数乘法器，3-2压缩，亲测可用-Wallace wrote the number 4 Booth algorithm unsigned multiplier, 3-2 compression, pro-test available
booth-multiplier
- 布斯乘法器设计源码。。功能完善，modelsim仿真通过-Booth Multiplier source. . Perfect function, modelsim simulation through
ParallelSerialMult
- 用verilog代码来实现并行序列乘法器，采用乘法器结构，读者可以自行编译，-Use verilog code to implement a parallel sequence multiplier, using the multiplier structure, readers can compile their own,
multier
- 流水线高速并行乘法器，流水线设计，并行加法计算-High-speed parallel pipelined multiplier
booth
- booth算法的乘法器设置及实现，使用VHDL语言编写-booth algorithm multiplier setting and implementation using VHDL language
QAM_FPGA
- QAM调制，基于FPGA的实现，包含有乘法器模块、升降余弦滤波器模块、QAM序列生成模块-QAM modulator,the implementation based on FPGA,include MUL、FIRCOS and QAM generate
mux16
- 该程序中中就是要利用时序逻辑设计方法来设计一个 16 位乘法器-The program is to take advantage of the sequential logic design method to design a 16-bit multiplier
mul_addtree
- 8位加法树乘法器Addition tree multiplier-Addition tree multiplier of 8bits
multiply
- verilog function实现全组合逻辑乘法器电路，位宽可配置，高效-Function purely combined logic circuit to achieve the function of the multiplier, configurable bit width, high efficiency.
fir25
- 用VDHL写的25阶对称FIR滤波器，在塞克隆3FPGA下验证没有问题（AD采样时钟50Mhz，这个对硬件设计有点要求），里面调用官方乘法器API，要节省资源可以采用CSD编码转换乘法器，可以减少一半以上的资源-VDHL written by a 25th order symmetric FIR filter in Seke Long 3FPGA under verify that no problem (AD sampling clock 50Mhz, this design is a bit