搜索资源列表
fenpin
- 时钟分频器，初学者可以下载学习，效果比较好-Clock divider, beginners can download the study results were quite good
81404600N_counter_VHDL
- 分频器一个n分频器的源代码任意N进制计数器标准代码写法-Divider divider of the source code of a n N binary counter any standard code written
ca60
- 60分频器，将主频分频，产生系统所需信号。-60 divider, the frequency divider to generate the necessary signal system.
xiyiji
- 洗衣机控制程序，包括分频器，计数器，触发控制器等。-Washing machine control procedures, including the divider, counter, trigger controller.
vhdl
- 3分频 器，LED分位译码电路，交通控制器，序列检测器-four programs based on vhdl
div_n
- verilog占空比50奇偶任意 奇偶任意分频器！包括测试代码-verilog random duty cycle of 50 odd parity arbitrary divider! Including test code
COUNT
- 设计一个最大分频为225的分频器，将50MHz时钟作为输入。分频器可以通过计数器来实现，通过一个25位的计数器，然后在最后一位输出，则产生了一个最大分频为225的分频器。-Design a maximum frequency divider 225, the 50MHz clock as input. Divider can be achieved through the counter, through a 25-bit counter, and then the last one out,
Crossover
- 分频器的设计，包含普通分频器和占空比为50 的奇数分频 ；4位乘法器的VHDL程序；-Crossover design, including general divider and the duty cycle of 50 of the odd frequency 4-bit multiplier VHDL procedures
zidongpinlv
- 4位自动换挡数字频率计设计 1、 由一个4位十进制数码管（含小数点）显示结果； 2、 测量范围为1Hz~9999KHz； 3、 能自动根据7位十进制的结果，自动选择有效数据的高4位进行动态显示（即量程自动转换），小数点表示是千位，即KHz； 4、 为检测设计正确与否，应将时钟通过PLL和手控分频器产生宽范围的多个频率来测试自动换档频率计功能。 -4 automatic transmission design a digital frequency meter, by a 4
jishufenpingqi
- 记数分频器 记数分频器 记数分频器-记数分频器记数分频器记数分频器记数分频器记数分频器记数分频器记数分频器记数分频器
EDA2
- 学习数控分频器的设计、分析和测试方法。数控分频器的功能就是当在输入端给定不同输入数据时，将对输入的时钟信号有不同的分频比，数控分频器就是用计数值可并行预置的加法计数器设计完成的，方法是将计数溢出位与预置数加载输入信号相接即可。-NC crossover study design, analysis and testing methods. NC divider function is that when the input given different input data, input th
div_fru
- 介绍分频器的好资料。不光有奇数分频、偶数分频，还有小数分频。相信把这个资料理解透了后以后分频器的设计就不是问题了。-Introduction divider good information. Not only have an odd frequency, even frequency, there are fractional. I believe understanding this information through the post after the Divider is not
frenquent
- 分频器的一些程序。包括整数分频，小数分频，我感觉非常好的资料，不敢私自分享。特拿出来分享。希望想学习的好好参考下，肯定会有所感悟。-Divider of some procedures. Including the integer frequency, fractional, and I feel very good information, not privately share. Point out to share. They want to study more carefully th
190.7_Freq_divider
- QUARTUS II环境下VHDL编写的小数点分频器程序，实现190.7分频，可以将50MHz时钟频率分频成约等于2^21Hz频率，方便特殊情况下的运算-QUARTUS II, prepared under the decimal divider VHDL program to achieve 190.7 frequency, you can divide into a 50MHz clock frequency is about equal to 2 ^ 21Hz frequency, eas
fenpinqi
- 分频器的一个例子，有源代码的，希望给大家带来帮助-Divider' s an example of source code, and I hope to give us help
div32
- 基于verilog的分频器 23分频器 可更具需要修改成任意偶数分频器-23 divider verilog-based crossover can be even more need to modify the divider into any
VHDLqiangdaqi
- VHDL四路抢答器该任务分成七个模块进行设计，分别为：抢答器鉴别模块、抢答器计时模块、抢答器记分模块、分频模块、译码模块、数选模块、报警模块，最后是撰写顶层文件。-VHDL four Responder divided into seven modules of the design task, namely: Responder identification module, timing module Responder, Responder scoring module, frequency
jiaocuofenpin
- 用硬件语言写了一个由8/9分频构成的无限不循环小数分频器，分频系数k=260/31-Written language with the hardware a 8/9 frequency divider consisting of an infinite non-recurring decimal, frequency factor k = 260/31
traffic
- 采用VHDL语言编写的控制交通灯工作的程序。分为四个部分：1，分频器，2，计数并产生控制信号，3，交通灯信号产生，4，交通灯总体描述。点击lzh6.aws打开工作空间-VHDL language used to control traffic lights work procedures. Divided into four parts: 1, divider, 2, count and generates control signals, 3, traffic signal generatio
freqdiv5
- verilog hdl 实现5分频器设计。