搜索资源列表
implementing_an_8_bit_asynchronous_interface_with_
- 2个Cy7c68013之间的GPIF与Slave FIFO异步通讯方案,以及源码-2 CY7C68013 between GPIF and Slave FIFO asynchronous communications programs, as well as source
Verilog
- 简易环形FIFO的设计、简单异步串行通信接口设计等-verilog
XR16M2550
- XR16M2550是一款高性能,具有16字节收发FIFO的异步全双工UART芯片,具有两路完全独立的UART通道。本资料包含完整的测试代码(ADS 1.2环境),中文应用文档,电路原理图,PPT讲解稿等。-XR16M2550 is a high-performance, with 16-byte receive FIFO, asynchronous full-duplex UART chip, with two-way completely independent UART channels.
SC28L198
- SC28L198是一个带有8个全双工异步通道UART的芯片,每个UART通道的接收器和发送器都拥有16字节深度的FIFO。芯片的每个UART通道除了基本的异步通信功能外,还可实现软件流控制(in-band flow control)、硬件流控制(out-of-band flow control)、以及多点模式(唤醒模式或RS-485模式)等,同时每个UART都有4个外扩的I/O引脚,每个外扩I/O引脚都为功能复用。 本资料包含完整测试程序,应用文档,电路原理图及PPT演示文档等。-SC28L
fifo2
- FPGA的异步先入先出程序,VHDL的fifo-VHDL and fifo
Chapter-9
- Verilog编写的异步串行FIFO程序,包括各种标志位,指针注释,其中还有SDRAM的读写程序-Asynchronous serial FIFO write Verilog procedures, including a variety of flag, pointer annotations, among them a SDRAM read and write procedures for
ASIC
- ASIC的异步时序设计,很有用,关于fifo-Asynchronous timing ASIC design, very useful
asy_FIFO
- 用Verilog实现FIFO的异步设计,里面有详细的代码和各个模块的代码,经过调试可以使用-asynchronous FIFO design
AVD
- 现代的IC芯片包含丰富的触发器,不同电路的时钟驱动源存在频率和相位的差异,因而出现了跨不同时钟区域进行异步数据传输的要求。亚稳态问题是异步数据传输过程面临的主要问题,本文提出多种跨越异步时钟边界传输数据的方法,它们包括FIFO法和脉冲展宽处理等同步方法。 -Modern IC chip contains a wealth of trigger, the clock drive source different circuit exists between the frequency and ph
LZY
- 基于FPGA的软FIFO代码实现,双时钟,异步。VERILOG-FPGA-based soft FIFO code, two clocks, asynchronous. VERILOG
FIFO_Asyn
- 这是异步的fifo程序,已经进过验证了,并且结果很不错,大家可以下载下来-this is fifo , and is already tested
68013A_BULK_TRANS
- CY68013A异步BULK传输范例,严格按照时序描述来进行读写,对fifo实现读写,功能完善。-CY68013A asynchronous BULK transmission model, in strict accordance with the temporal descr iption to read and write, read and write to the FIFO implementation, perfect function.
FIFOUART
- fpga实现的基于FIFO的异步串行通信代码,描述语言为Verilog-fpga-based FIFO asynchronous serial communication code descr iption language Verilog
Tx_state
- 应用于实时以太网通信,通过高速FIFO实现异步时钟域通信,通过状态机实现FIFO操作,实现与物理层芯片通信。-Used in real-time Ethernet communication, asynchronous clock domain communication speed FIFO FIFO operation state machine, with the physical layer chip communication.
uart_fifo_design
- verilog语言时序的异步读写FIFO,请需要者借鉴参考-the verilog language Timing asynchronous read and write FIFO, for those who need to learn from reference
uartfifo
- FPGA采用FIFO实现UART,对于大量异步数据的采集传输很有帮助-A usart design of FPGA using fifo,it can be used in massed asychronous data collect.
camera_fifo_ctrl
- camera异步接口中FIFO控制部分的源代码-FIFO control section of the source code in the asynchronous interface, camera
series_rxd_timing
- 接收异步串口数据,将数据写到接收fifo中,可设置超时来接收多字节数据,当设置超时时间内未出现数据,ready信号有效,表示接收完整数据包,可从fifo中读取数据。-Receive asynchronous serial data, the data is written to the receiving fifo, you can set the timeout to receive multi-byte data, set the timeout period when the data d
Philips_SC28L198A1A-S9203
- NXP 28L198 8路UART是一个单芯片的CMOS-LSI通信器件,它提供8路全双工异步通道,具有16字节FIFO,使用用户定义的Xon/Xoff字符可以实现自动带内(in-band)流控制,唤醒模式下可以进行地址识别。所有主机和OCTART之间的通信都使用同步总线接口。它由NXP 1.0微米的CMOS技术制造而成,结合了低成本、高密度和低功耗的优点。-NXP 28L198 8-channel UART is a single-chip CMOS-LSI communications de
myuart
- 使用verilog语言编写的异步串口模块,带有16级深的FIFO,它与DSP28335的SCI相似,可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路-Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and