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paobiao
- 实现数字跑表功能,该跑表具有复位、暂停、秒表计时等功能。-Digital stopwatch function, the stopwatch with a reset, pause, stopwatch timer functions.
digitalpaobiao
- 用Verilog HDL语言编写的数字跑表源程序,已经通过综合编译及仿真。-With the Verilog HDL source code written in digital stopwatch has been through a comprehensive compilation and simulation.
EDAshiyanbaogao
- 关于VHDL的关于数字跑表的eda的课程设计!-failed to translate
paobiao
- 基于Verilog HDL的完整数字跑表工程,在试验机台上运行验证通过了的。 用8位7段数码管分别显示微妙,秒,分。 有开始,暂停,复位功能。 学习VerilogHDL的经典例子,添加了显示功能。-Complete Verilog HDL-based digital stopwatch works in the test machine is running verify pass the platform. With 8-bit 7-segment digital tube sho
shuzipiaobiao
- 数字跑表的60,100模计数器,2个模60,一个模100组成功能模块-mod60,mod100,count,EDA
code
- 这是一个数字跑表的代码,用FPGA实现的,对大家或许有用-This is a digital stopwatch in the code, FPGA implementation, perhaps all of us
paobiao
- 该程序是用verilog语言实现的数字跑表功能,其中分为计数模块与数码管显示模块。-The program is verilog language digital stopwatch function, which is divided into counting module with digital display module.
digital-clock-
- 本代码采用verilog HDL语言编写。实现的是数字跑表计时功能-The code using verilog HDL language. Implementation is a digital stopwatch timer functions
shuzipaobiao
- 在ISE环境下用Verilog HDL写的一个简易的数字跑表,最大量程为60分钟,精确到毫秒级,有复位键和暂停键。-In the ISE environment, using Verilog HDL to write a simple digital stopwatch, the maximum range is 60 minutes, accurate to the millisecond, the reset button and pause button.
shuzipaobiao
- 一个关于数字跑表的小程序代码,verilog实现,并通过仿真。-A digital stopwatch on a small code, verilog implementation, and simulation.
shuzipaobiao
- 设计一个数字跑表,该跑表具有复位,暂停,秒表计时功能,暂停后恢复时,在原来数值基础上继续计数-Design a digital stopwatch, the stopwatch has reset, pause, stop watch timing function, recovery after a pause, continue on the basis of the original value of count
stopwatch_verilog
- 数字跑表 verilog语言设计有开始 有暂停 顺序计数-stopwatch verilog
paobiao-_verilog
- 数字跑表,硬件表述语言Verilog 实现,测试功能全 -Digital stopwatch, expression language Verilog hardware implementation, testing, full-featured
MyTimer
- 电子表功能描述 电子表共有5种功能:功能1为数字钟;功能2为数字跑表;功能3为调时;功能4为闹钟设置;功能5为日期设置。除调时功能以外,电子表处于其他功能状态下时并不影响数字钟的运行。使用数字钟功能时,还可以通过按键快速查看当前的闹钟设置时多功能间和当前日期。该电子表利用EDA实验平台的扬声器整点报时和定时报时,设置3个按键分别作为功能键和调整键。 -Functional descr iption of electronic clock: Electronic clock has a
watch
- 基于DE-2的数字跑表设计,并带两种显示功能-DE-2-based digital stopwatch design, with two display
paobiao
- 数字跑表,包含百分秒、秒、分,能在FPGA上下载并显示-Digital stopwatch, including hundredths of a second, seconds, minutes, can be downloaded and displayed on the FPGA
stopwatch-shuzipabiao
- 在FPGA下实现分频、计数、显示功能。 数字跑表-Divider in FPGA, counting and display functions. Digital stopwatch
paobiao
- 这个程序是用verilog语言下的数字跑表实验,经测试,好用。-This program is a digital stopwatch experiments under the verilog language, tested, easy to use.
Digital-Clock
- FPGA数字跑表代码 Digital Clock-Digital Clock
number_clock
- 典型实例 用FPGA来开发一个 数字跑表,实现跑表的全部功能-FPGA Verilg clock