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SHUZIZHONG
- VHDL语言编写的数字钟程序,在quartus软件下编写。-VHDL language digital clock program, prepared in quartus software.
sy
- 利用VHDL语言设计的电子数字钟,有时、分钟、秒钟计数器、还有整点报时报警。-Design using VHDL language electronic digital clock, sometimes, minutes, seconds counter, as well as the whole point timekeeping alarm.
clockhms
- 自己写的数字钟源程序,VHDL语言,50M晶振,24小时计时制,可以清零,较时,闹钟。-I design a 24hr clock set, VHDL language, 50M crystals, it can be reset, relatively, the alarm clock
shuzizhong
- vhdl数字钟通过fpeg仿真实现vhdl实验课设 -vhdl digital clock
component_timer_counter
- Quartus环境下基于VHDL元件例化的数字钟程序-Zhong Chengxu digital VHDL component instantiation based on Quartus environment
shuzizhong
- 数字钟,校时较分,显示,用元件例化写的vhdl文件,两个24进制,1个60进制计数器-Digital clock, when the school over the points, show cases with elements of writing vhdl file, two 24-band, a 60-ary counter
the-digital-clock
- 本设计选用 ALTERA 公司的 EP1C12Q240C8 芯片,利用 VHDL 语言采用自 顶向下的方法在 Quartus Ⅱ环境下完成了数字钟的设计,最后在实验箱上进行测 试。该数字钟包含的功能有计时、显示星期、校时校分、清零、整点报时、音乐 闹铃。-The design uses the silicon chip EP1C12Q240C8 produced by the company of ALTERA. And with the help of VHDL, the de
digitalclock
- 数字钟 初学VHDL时可参考 模10状态机 83译码器-Refer to die 10 when the state machine 83 decoder VHDL digital clock beginner
dig_clk
- 实现vhdl数字钟 实现时分秒调时 消抖等功能 采用quartus编程实现 -digital clock
digital-clock
- 用FPGA实现数字钟功能,用VHDL语言编写,含有课程设计报告-FPGA digital clock
shuzizhong
- 在ise平台上用VHDL语言实现数字钟,具有计时和重置时间功能、整点报时功能、闹钟功能,每个功能都使用元件例化的方法,通过顶层文件将每一个模块联系在一起。-On ise platform using VHDL digital clock with timer and reset the time function, the whole point timekeeping function, alarm clock function, each function using the compone
shuzizhong
- 基于VHDL语言的数字钟,有元件例化,修改时钟功能 Quartus II平台-VHDL language based digital clock, there are component instantiation, modify clock function Quartus II platform
Digital-clock
- 设计一个数字钟,使用vhdl语言进行编写,以上是源程序-The design of a digital clock, using VHDL language, the above is the source
EDA
- EDA实验程序:60进制,数字钟 ,表决器 包括VHDL语言和图的连线-EDA experimental procedure: 60 binary, digital clock, voting Including connection VHDL language and graphs
cpld
- CPLD与电子CAD报告 VHDL中的并行语句、进程 信号、变量、顺序语句 分频器、计数器、译码器、状态机 数字钟综合设计-CPLD and VHDL electronic CAD report in parallel statement, the process signals, variables, sequential statements divider, counter, decoder, an integrated digital clock state machine des
szz
- 基于CPLD的数字钟,用VHDL语言编写,数码管显示,可调时调分,具有整点报时功能。-CPLD-based digital clock, using VHDL language, the digital display, an adjustable transfer points, the whole point timekeeping function.
VHDL_doc
- VHDL入门的程序,包括数码管显示,交通灯的实现,多功能数字钟,数字频率计等-VHDL entry procedures, including digital display, realize traffic lights, multifunction digital clock, digital frequency meter, etc.
FPGA
- 数字钟的VHDL语言程序,包含了好几个模块,是毕业设计的优秀程序,值得下载!-VHDL language program of digital clock, contains several modules, is an excellent program, graduation design is worth to download!
clock
- VHDL语言,数字钟实现时分秒计数,能够通过按键调整时间-VHDL language, when every minute counts achieve digital clock, the time can be adjusted through the key
clock
- 用VHDL 语言设计数字钟,实现在数码管上显示分钟和秒,并且可以手动调节分钟, 实现分钟的增或者减。该设计包括以下几个部分: (1)分频电路的设计,产生1Hz 的时钟信号,作为秒计时脉冲; (2)手动调节电路,包括“时增”“时减”“分增”“分减”。 (3)时分秒计时电路。 (4)7 段数码管显示电路。 将 SW1 和SW2 初始状态均置为高电平。拨动开关SW1 到低,分钟进行加计数,秒停 止计数,当计数到59 时,从00 开始重新加计数,将SW1 拨动到高时,在当前状