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RISC_CPU
- 一个32位流水线 CPU 设计， 含设计文档和模拟图。-A 32-bit pipelined CPU design, including design documentation and simulation in Fig.
pipelined_computer
- 基于de2-board的汇编以及verilog的五段流水线CPU代码，适合新手学习-Based on the de2-board assembler, and the five-stage pipelined CPU verilog code, suitable for novice learning
mips-cpu
- 一个组成原理的课程设计，完成一个流水线MIPS CPU的设计，有详细的说明及其代码，实测可用-a project about the design of MIPS CPU
CPU
- 流水线简单CPU设计，基于简单的数字系统设计，为verilog语言，电路设计基于基本的数字电路-Pipelined CPU design, design of digital system based on a simple, Verilog language, based on the basic digital circuit design
pipline
- 用verilog实现的流水线cpu,实现高效率的CPU基本运算-Pipeline cpu with verilog
PipelineCPU
- 这是我们设计的一个MIPS流水线CPU，基于Verilog HDL语言实现。它与传统的MIPS流水线CPU不同点在于，5个流水段各自维护一个变量(SelType)表明当前正在执行的指令类型，这样处理数据冒险、loaduse冒险或者跳转冒险时候每个段都能知道其他段正在处理的语句，从而方便我们的处理。-This is a MIPS pipelined CPU based on Verilog HDL language to achieve. It the the MIPS pipelined CPU
CPUv1.6
- 简单的流水线CPU 课设做的 有实验报告 跟设计图-Simple pipelined CPU Lesson set up a lab report with design
piplelinecpu
- 流水线CPU，实现MIPS简单指令的运行，在XLINX实验板上运行-Pipelined CPU, MIPS simple instructions to achieve the operation, run in XLINX experimental board
logic-design-of-CPU
- 本文献介绍了基于32位架构的双发射流水线设计。-design of 32bits CPU
CUP
- 流水线cpu，简单的CPU，但是功能俱全-Pipeline cpu
RISC-CPU-
- 用VHDL语言实现32位CPU的各种运算功能，熟悉32位CPU各模块的工作原理，熟悉流水线数据通路和控制单元的工作原理从而熟悉CPU的工作机理。-Mac circuit realization
VHDLCode_8bitCPU
- 这是计算机组成原理的课程设计，将16位CPU改造成8位流水线CPU，AHDL语言，这是改造完成的源代码。-This is a computer composition principle of curriculum design, the 16-bit CPU transformed into eight pipeline CPU, AHDL language, which is the transformation was complete source code.
MIPSCPUverilog
- mips流水线CPU的实现，用的是verilog语言，描述了整个cpu的过程。存储、指令、处理等。-mips CPU Verilog
SRC
- 流水线CPU的verilog实现，包含id，if，ex，mem等部分的源码-an implementation of Pipelined CPU in verilog
cpu
- cpu流水线代码，完整实现所有指令，包含top顶层文件的实现和仿真代码-cpu lines of code, complete implementation of all the instructions, including the implementation and simulation code top top level file
CPU
- 五级流水线.期末的project,写了很详细的注释，应该能看得懂了吧。-Five-stage pipeline. Closing the project, wrote a very detailed notes, should be able to understand it.
cpu
- vhdl实现处理器基本功能，不包括流水线-VHDL to achieve the basic functions of the processor
mips
- Verilog语言开发的基于mips指令集的流水线cpu，只支持部分指令-Verilog language-based development pipeline cpu mips instruction set support only part of the instruction
Code1
- 拥有提前判断，和假设分支条件不满足的流水线CPU- Pipeline CPU with forwarding and predict-not-taken
pcpu_handle_mem
- Verilog实现五级流水线CPU，hazard以及时序功能已经实现。-Realize five-stage pipeline CPU