搜索资源列表
PipelineCPU2
- Modulsim下Verilog写的五级流水线32位简易CPU-five level pipeline CPU written in Verilog.
Lab9-Forwarding-Unit
- CSCE2214课程设计，试验9源代码。实现流水线结构的MIPS CPU 16位。配有强大的Forwarding Unit.-CSCE2214 curriculum design, test 9 source code. Implement pipelined MIPS CPU 16 place. With a strong Forwarding Unit.
PipelineCPU
- 设计一个32位流水线MIPS微处理器，具体要求如下： 1. 至少运行下列MIPS32指令。 ①算术运算指令：ADD、ADDU、SUB、SUBU、ADDI、ADDIU。 ②逻辑运算指令：AND、OR、NOR、XOR、ANDI、ORI、XORI、SLT、SLTU、SLTI、SLTIU。 ③移位指令：SLL、SLLV、SRL、SRLV、SRA。 ④条件分支指令：BEQ、BNE、BGEZ、BGTZ、BLEZ、BLTZ。 ⑤无条件跳转指令：J、JR。 ⑥数据传送指令：LW、SW
pipeline_cmd
- 这是用Python实现的16位cup的代码 其中提供了流水线与分支预测的功能 如果你有在学习计算机原理或者体系结构的话，研究和实现这些源码对你的知识架构很与偶帮助-This archive File includes the code to simulate the 16bit cpu. We use Python to implement our design. In the CPU pipeline and branch estimate technique is added. If
pipeline10
- 用verilog实现嵌入式系统的处理器的五级流水线。-realizing the five stages of cpu in the embedded system with the verilog language
cpu_design
- FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告-FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language
computer-composition
- Verilog在FPGA上实现多周期流水线带forwarding和hazard检测(如果你是学弟，为你着想，请不要直接copy)-Verilog on FPGA implementing a multi-cycled CPU with forwarding and hazard test
CPU_Project_board
- CPU 5级流水线实现（加hazard处理与板级验证，板级验证带有按键消抖）-5-stage pipelined CPU (plus hazard dealing with board-level verification, board-level verification with key debounce)
jiemr480
- 可以获得CPU的缓存大小,流水线数等等30多项CPU的特性-Can get the CPU cache size, number of lines and so on more than 30 characteristics of the CPU
1266318
- 可以获得CPU的缓存大小,流水线数等等30多项CPU的特性-Can get the CPU cache size, number of lines and so on more than 30 characteristics of the CPU
Can_chaqacteristacs_bore
- 可以获得CPU的缓存大小,流水线数等等30多项CPU的特性(Can get the CPU cache size, number of lines and so on more than 30 characteristics of the CPU)