搜索资源列表
mile
- 密勒码最初用于气象卫星和磁记录,现在也用于低速基带数传机。本文件是密勒码解码源码。-For wireless RFID code decoding circuit of the Miller
H.264
- 关于h.264视频解码器完全源码(verilog)-With regard to h.264 video decoder full source code (verilog)
mp3
- MP3音频解码的verilog源代码,已经验证过的,可综合-MP3 Audio coding
mp3decoder
- verilog实现mp3解码程序,包括testbench-mp3 decoder verilog implementation procedures, including the testbench
CMI
- 基于FPGA/CPLD的CMI编解码设计,含程序说明及仿真截图。-Based on FPGA/CPLD' s CMI codec design, including descr iption of the procedures and simulation screenshot.
H.264Decoder
- H.264解码器,用verilog写成,可以在FPGA上实现baseline的264解码-H.264 decoder, written with verilog, can be achieved in the FPGA on the baseline of 264 decoding
8b10b_pdf
- 8b10b编解码设计的pdf文章,用于现代千兆网通信,快速串行通信.-.pdf paper
VERILOG-jpeg
- 用Verilog语言在FPGA上实现JPEG图片的解码,附带testbench-With the Verilog language in the FPGA to achieve JPEG image decoding, with testbench
turbodecoder
- 用vhdl实现turbo码的迭代解码,转某N人的程序-Using vhdl implementation of iterative decoding turbo codes, transfer of a person' s procedures for N
MP3_in_CycloneII
- 在FPGA中实现MP3的解码,verilog的,带说明文档。-In the FPGA to implement MP3 decoding, verilog, and with documentation.
cmi
- CMI/AMI编码解码模块 VHDL源代码-CMI/AMI编码解码 VHDL源代码
pcm
- 基于FPGA的PCM编码器与解码器的设计-about fpga and pcm
interpolator
- 插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现-Interpolation filter, audio decoder for modulation and demodulation, filter coefficient shift combined with the realization of
Mpeg4
- Mpeg4编解码,好不容易在国外网站上找到的源代码-Mpeg4 codec, hard to find in the foreign site
1553_enc_dec
- 1553b的编解码源程序 和仿真程序,fpga来实现的 vhdl语言 -1553B codec source code and simulation procedures, fpga to achieve the VHDL language
husw
- 用VHDL语言设计维特比 解码器 是VHDL原代码用ModelSim XE III 6.3c软件实现仿真-Language Design with VHDL Viterbi decoder is the VHDL source code with ModelSim XE III 6.3c software simulation
PlayDemo
- VC写的h.264规范解码程序,具体看程序注释-VC norms h.264 decoding written procedures, specific procedures see Notes
video_process_base_on_DSPandFPGA
- 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型 化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间 利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管
rs-codec-8-16
- RS[255,223]纠错码verilog源码,包含编码和解码模块,以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
ldpc
- 最近在做毕设,ldpc码的编解码实现,这个是verilog实现。-Recently completed the set up to do, ldpc code codec implementation, this is the Verilog implementation.