搜索资源列表
SpW_codec_perfect
- SpaceWire 编解码器完整验证，vhdl源程序，-SpaceWire compile a complete verification of decoder, VHDL source code,
pcm
- ２４选８多路选择计数器 PCM编解码,采编器VHDL 源代码，包括顶层文件。-PCM(Pule code modulation) code and decoder
b8b__10bbi
- vhdl开发，8b—10b 编解码器设计Encoder: 8bb/10b Encoder (file: 8b10b -vhdl development, 8b-10b codec design Encoder: 8bb/10b Encoder (file: 8b10b
QDEC
- 旋转编码器的正交解码程序，使用VHDL语言--- This decoder in VHDL samples the signals using all four available edges of -- A and B. E.g. sample(B) on rising(A), sample(A) on falling(B), sample(B) on -- falling(A), and sample(A) on rising(B).
decoder_1553
- quartus软件编写，1553总线解码程序，采用vhdl语言-the quartus software written 1553 bus decoding procedures, vhdl language
FSK
- vhdl编写的FSK编码器与解码器，绝对可用，拿去用吧。 -the FSK encoder and decoder VHDL written, absolutely free, and take with you.
FPGA_of_CMI
- 基于FPGA的CMI编码和解码程序，采用VHDL语言设计，通过了仿真验证。-FPGA-based CMI coding and decoding procedures, using VHDL language design, through simulation.
cmi
- 运行于Altera Cyclone FPGA平台,由VHDL编写的NRZ到CMI编码和CMI到NRZ解码程序。-Running on Altera Cyclone FPGA platform, VHDL prepared NRZ to CMI CMI to NRZ encoding and decoding procedures.
Manchester
- 运行于Altera Cyclone FPGA平台,由VHDL编写的NRZ到曼彻斯特编码和曼彻斯特编码到NRZ解码程序。-Running on Altera Cyclone FPGA platform, consisting in VHDL coding NRZ to Manchester and Manchester encoding to NRZ decoding process.
Verilog
- VHDL Verilog 系统仿真实验 流水灯 加减法 计数器 序列检测 编码器 解码器等-VHDL Verilog 系统仿真实验 流水灯 加减法 计数器 序列检测 编码器 解码器等
8b_10b
- 8B10B 编解码实现 用VHDL实现的-8B10B encoding decoding
hamming
- 32位海明码编码解码的vhdl代码，有testbench验证。-32 Hamming code encoding and decoding of vhdl code, testbench verification.
mb_rcver
- vhdl，1553b接收模块，为以后的解码和过滤提供稳定的输入。-the 1553b receiver mode, provide a proper input for the 1553b s caodec and fliter
ldpc-decoderVHDL
- 采用VHDL实现LDPC码的编解码过程，有一定的参考价值，希望对大家有帮助-Use VHDL to realize the decoding process of LDPC code has a certain reference value, hope to help everyone
decode1
- 只是汇编语言VHDL所实现的解码器的功能，可以实现解码的功能-this is the language of VHDL， it can realise the function of decode
IRIGDECODE
- IRIG-b 解码模块 采用VHDL编写，简单实用，已实测验证-IRIG-B DECODE VHDL
decoder
- 采用VHDL语言输入法，根据HDB3码编解码规则，确定HDB3码编画出HDB3码的程序设计流程图。编写VHDL源程序、调试及仿真时序波形 -Using VHDL language input method, according to the HDB3 encoding and decoding rules that determine HDB3 code HDB3 encoding and draw a flow chart programming. Write VHDL source co
CAVLE-h264
- 本压缩文件包含了h.264压缩算法中的CAVLE的编解码模块（Verilog和VHDL两个版本），包含有仿真的testbench测试文件，综合后可以直接使用-The compressed file contains the h.264 compression algorithm CAVLE codec module (Verilog and VHDL both versions), including a simulation testbench test file, can be used d
CC
- 802.16d 的卷积编码和解码的VHDL实现-802.16d cc encoding and decoding,writing in VHDL
RS
- 802.16d的RS编解码的VHDL实现-802.16d RS encoding and decoding in VHDL