搜索资源列表
decoder3_8
- 通过vhdl语言来实现简单的3--8译码器的制作-Vhdl language to achieve through a simple 3- 8 decoder making
controlvhdl
- 一个四位微程序控制器的指令译码器源码，运用VHDL语言实现。-A four micro-program controller instruction decoder source code, the use of VHDL language.
chenxu
- 3—8译码器是由8个3输入“与非”门构成，采用VHDL语言描述，从行为、功能对3—8译码器进行描述，不仅逻辑设计的容易，而且阅读方便。-3-8 decoder input by 8 3 " and not" the door structure, use of VHDL language descr iption, from the behavior and function of the 3-8 decoder is described, not only the logic
TAXI
- 基于VHDL的出租车计费器，通过VHDL语言来编程实现计费系统的四个功能块：分频模块，控制模块，计量模块和译码显示模块，最后使用MAX+PLUSII软件来对程序进行仿真，以模拟实现出租车的启动，停止以及等待等过程中的计时，计程和计费功能。-Taxi meter based on VHDL, VHDL language programming through the billing system of the four functional blocks: frequency module, co
count
- 1．用VHDL设计具有清除端、使能端，计数范围为0~999的计数器，输出为8421BCD码； 2．用VHDL设计十进制计数器（BCD_CNT）模块、七段显示译码器电路（BEC_LED）模块和分时总线切换电路（SCAN）模块。 3．用MAX+plusⅡ进行时序仿真。 -1. VHDL design with a clear end to end so that the count range of 0 to 999 in the counter, the output is 8421B
decoder
- mp3译码器的实现，在fpga上实现多媒体功能-this project is the mp3 decoder， designed by vhdl
38encoder
- 通过vhdl语言编写的38译码器，并用quartus进行设计-Written by vhdl decoder 38 and designed with quartus
Design_74LS138
- 利用Active-VHDL 来仿真测试74LS138 译码器，74LS138 译码器是3 线-8 线译 码器。-To the use of Active-VHDL simulation test 74LS138 decoder, 74LS138 decoder is a 3-wire-8 line decoder.
decoder_3_to_8
- 在Quartus II 中用VHDL语言编写的3-8译码器程序-In the Quartus II VHDL language using 3-8 decoder program
15Turbo
- urbo码是1993年法国人Berrou提出的一种新型编码方法。它巧妙的将卷积码和随机交织器结合在一起；同时，采用软输出迭代译码来逼近最大似然译码-urbo code is 1993 French Berrou proposed a new encoding method. It is clever to convolutional codes and random interleaver together the same time, the use of soft-output itera
yimaqi
- 用VHDL实现3-8线译码器的功能，即74HC138-3-8 lines with the VHDL implementation of the decoder function, which 74HC138
led
- 流水灯的VHDL程序 晶振6MHZ,里面包含分频部分与3线八线译码器-LED FLOWS
exp1.3_decoder3_8
- 用VHDL及verylog语言实现3_8译码器的功能，可以在Quartus II上实现-Using VHDL and verylog language 3_8 decoder function, you can achieve in Quartus II
seg
- 六位十六位进制数可逆循环计数器、七段译码器设计，完全有VHDL语言设计，生成SYM文件后，设计top.gdf文件，赋好管脚下载到altera芯片上执行。-Sixteen decimal six reversible cycle counter, seven-segment decoder design, fully VHDL language design, build SYM files, design top.gdf file, assign a good pin downloaded to
easy_vhdl
- 一些常用的VHDL代码，包括逻辑门，寄存器，译码器，数据选择器，触发器- Some common VHDL code, including logic gates, register, decoder, data selector, trigger, etc.
clock
- 数字秒表计数 vhdl 译码器 分频器 计数器 报警器-stopwatch counter
38yimaqi
- 学习设计一个3/8译码器，并在实验板上验证； 2．学习使用VHDL语言进行逻辑设计输入； 3．学习设计仿真工具的使用方法； -Learning design a 3/8 decoder experiments, the board validation 2. Learn to use VHDL language to logical design input 3. Learning design simulation tools using methods
decode38
- 通过使用VHDL语言的程序编写实现38译码器的功能-Through the use of VHDL language programming to achieve the 38 decoder functions
Hex_decoder_7seg
- 十六进制显示译码器，VHDL语言的设计，根据高低电平的变化进行数码管的数字显示-Hexadecimal display decoder VHDL language design, high and low changes in the number of digital tube display
38
- 3-8译码器的vhdl源程序，设置了3个输入端s1,s2,s3-3-8 decoder vhdl source code