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Count-display-circuit-design(VHDL)
- 用VHDL语言设计计数显示电路。设计输出为3位BCD码的计数显示电路。由三个模块构成：十进制计数器（BCD_CNT）、分时总线切换电路（SCAN）和七段显示译码器电路（DEC_LED）-VHDL language to count the display circuit. The design output for display circuit 3 BCD count. Consists of three modules: the decimal counter (BCD_CNT), time
VHDL
- 本程序是些用VHDL应用的一些基本程序，有分频器，编译码器等一些基本器件程序-This program is using VHDL applications, some of the basic program, a divider, codecs, etc. some of the basic device program
3-8decoder
- 3_8译码器,vhdl语言编写,使用在fpga板子上,原始代码.-3_8 decoder, vhdl language written in use in the fpga board, the original code.
Seven-Segment-LED-Decoder
- 简单的七段数码管译码器vhdl程序,比较基础,适合初学者练习使用-Simple seven-segment decoder vhdl program basis for comparison, for beginners to use.
vhdl_code
- 用VHDL语言设计实现一个74LS138/8位移位寄存器译码器。-74LS138——code
VHDL
- 一些简单基本的vhdl代码源程序，包扩三八译码器，数据选择器，30s倒计时器等-Some simple basic VHDL source code procedures, bag expanding 38 decoder, data selector, 30 s down timer, etc
vhdl
- 行为描述、数据流描述、结构描述实现2to4译码器。-Behavior descr iption, descr iption of the data stream, 2to4 decoder schema.
VHDL
- 74LS161 JK触发器带清0端,项目名称为dff_JK_111 十进制计数器74LS290,项目名定为CTLS290：运算方法编写的290计数器：另一种编法LS290 不带使能端的3线8线译码器 八选一数具选择器：用CASE语句 全加器： 简单的JK触发器-74LS161 JK flip-flop with cleared end Project Name dff_JK_111 decade counter 74LS290 project name as CTLS290: and comp
sxbxymq_t15
- 3线8线译码器vhdl实现的，很好用，希望初学者好好看看！-3 lines and 8 line decoder vhdl, good with beginners a good look!
Experiment
- 可编程逻辑器件VHDL实现的3线-8线译码器-VHDL 3-8 priority encoder decoder
188135a9844b
- rs(204,188)译码器VHDL语言源代码-failed to translate
VHDL
- 3-8译码器 4-2优先编码器 4选1多路选择器-3-8 4-2 priority encoder decoder 4-to-1 multiplexer
vhdl.tar
- 38译码器的VHDL实现，支持linux平台，包含完整的Makefile支持。-38 decoder VHDL, support linux platform, including full Makefile support.
VHDL
- 四选一电路,分钟计数器，三八译码器，先进先出-Four elected a circuit, VHDL procedures VHDL procedures VHDL procedures VHDL program
VHDL-code
- 使用VHDL语言进行门电路，优先编码器，译码器，各进制计数器，数码管显示的编写，在QUARTUS ii上模拟可用-Gates using VHDL language, priority encoder, decoder, each binary counter, write digital display, analogue available on QUARTUS ii
VHDL
- 组合逻辑电路设计：基本逻辑门、三态门、译码器。-Combination logic circuit design: basic logic gates, tri-state gate decoder.
vhdl
- 用计数器、3/8译码器和门电路设计序列信号发生器用示波器观察并测量波形。-Counter, 3/8 decoder circuit design sequence and doors to observe and measure the waveform signal generator with an oscilloscope.
vhdl
- 译码器设计 实现3-8译码器的门级和行为级设计；完成3-8译码器的门级和行为级设计的仿真，并下载到开发板进行验证。 用拨挡开关K1，K2，K3作为输入的三位二进制码，输出的8位码分别用LED1~LED8 显示-Achieve 3-8 decoder gate-level and behavioral level design complete the 3-8 decoder gate-level simulation and behavioral level design, and d
VHDL
- 数字电路中常用的3线-8线译码器及8线-3线优先编码器的VHDL语言的功能描述-That is commonly used in digital circuit lines to 3-8 8 line to 3 line priority encoder decoder and the function of the VHDL language descr iption
VHDL-Programming-Examples
- 分频器、译码器、编码器、计数器、状态机等基本的硬件描述语言代码-The basic hardware divider, decoders, encoders, counters, state machine descr iption language code