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38yima
- 本文为用vhdl语言编写的38译码器，为doc格式，请先复制到相应软件例如maxplus中再使用。-This article was prepared by using VHDL language decoder 38 for doc format, please copy to the appropriate software such as maxplus in the re-use.
dec3_8
- 有VHDL写的一个38译码器,并付仿真波形.-VHDL has written a decoder 38, and pay the simulation waveform.
Decoder_FPGA
- 这是Actel 的FPGA的译码器的VHDL源代码。-This is the Actel' s FPGA-Decoder VHDL source code.
bym
- 在Max+plusΠ环境下用VHDL语言编写实现基于CPLD的CMI编译码器设计-In Max+ plusΠ environment using VHDL language CPLD-based design of CMI codecs
7decoderdesigndigitaldisplay
- 1.学习7段数码显示译码器设计。 2.进一步熟悉VHDL设计技术,掌握CASE语句的使用。 3.掌握文本输入法的顶层设计方法。 -1. Learning 7 decoder design digital display. 2. More familiar with the VHDL design techniques, master the use of CASE statements. 3. Have the text input method of the top-level d
lab2-2
- 4位二进制加法器，vhdl实现,外带译码器部分，清晰简洁，可读性好-4-bit binary adder, vhdl achieved decoder part of the bargain, clear and concise, readable good
MY
- 计数器和译码器的程序，基于EDA的VHDL语言-Counter and decoder procedures, based on the VHDL language EDA
control
- 四位微程序控制器的指令译码器，运用VHDL语言实现。-Four micro-program controller instruction decoder using VHDL language.
hdb3
- 基于vhdl的hdb3编译码器的设计与实现-hdb3
counter
- 利用EDA工具MAX-PlusII的VDHL输入法，输入VHDL程序，实现2位计数器，在七段译码器上以十进制显示：0、1、2、3、0、...。时钟信号使用83管脚。采用自动机状态转换方式设计该计数器；建立相应仿真波形文件，并进行波形仿真；分析设计电路的正确性。-The use of EDA tools VDHL of the MAX-PlusII input method, enter the VHDL program, the realization of two counters, in t
shujujiegou
- 数自逻辑实验报告有关于83译码器的编写，用VHDL编写程序-Since the logic of the report of the number of experiments on the preparation of 83 decoder using VHDL programming
VHDLCODE
- VHDL的一些典型源代码，有七段数码管译码器，格雷码转换为二进制码，八位数字比较器等等。-Typical VHDL source code, there are Seven-Segment LED Decoder, Gray code is converted to binary code, the eight figures and so on.
00038yimaqi
- 本设计利用拨动开关和发光二极管进行信号输入和显示。 本设计练习用VHDL语言描述仿真译码器。 -This design toggle switch and light-emitting diodes used for signal input and display. The design exercise simulation using VHDL language to describe the decoder.
taxi
- 介绍了出租车计费器系统的组成及工作原理，简述了在EDA平台上用单片CPLD器件构成该数字系统的设计思想和实现过程。论述了车型调整模块、计程模块、计费模块、译码动态扫描模块等的设计方法与技巧。-Introduced a taxi meter system, the composition and working principle outlined in the EDA platform, with the single-chip CPLD devices constitute the digit
3
- 利用vhdl语言编写的译码器程序，采用两种不同方式-The use of language decoder vhdl program, using two different ways
recover
- VHDL设计的HDB3的译码器，采用了四位移位寄存器来判断之前码元1/0，造成输出有5位时延。-VHDL design of HDB3 decoder, using four yards before the shift register to determine the yuan 1/0, resulting in output has five delay.
vhdltest
- 自己设计的几个VHDL程序，包括译码器电路，多路开关，比较器应用，和16乘8RAM电路，各模块及最终的顶层原理图和引脚我都已给好，希望对大家的学习有所帮助-A few of their own design VHDL procedures, including the decoder circuit, multiple switches, comparator applications, and 16 by 8RAM circuit, each module and final top-leve
paobiao
- 数字跑表，VHDL语言描述，已经过实验,包含有分频计、计数器，显示译码器-It has been tested,and it is described by VHDL.
S1_38yima
- 3-8译码器的VHDL语言实现的源程序代码-3-8Decoder
HDB3
- HDB3编码器与译码 HDB3编码器与译码-HDB3 encoder and decoder