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Desktop
- VHDL code for 16 byte ROM & n bit comparator & a full adder
brentkung_16
- 16位的brentkung加法器树，在xilinx软件下-16-bit brentkung adder tree, under the xilinx software
adder4-7seg
- 这段程序主要是实现了两个16进制的数据相加减，主要思想是由32位的进位加法器的来。目标板是spartan 3的实验板。-This program is to achieve a two-phase addition and subtraction of data 16 hex, the main idea is to carry the 32-bit adder to. Target board is spartan 3 development board.
lab
- verilog语言设计同步加法器，异步减法器，16位计数器-adder verilog language design synchronous, asynchronous subtractor, 16-bit counter
complement_adder
- 十六位补码加法器，输入为两个16位补码，输出和为17位补码，不虚溢出标志。-Sixteen complement adder, the input to complement the two 16-bit, output, and for the 17 complement, not virtual overflow flag.
add32
- 16位DSPTMS320F2407实现32位加法源程序-16 DSPTMS320F2407 source 32-bit adder
adder16
- 16位全加器，适合初学者用，上实验课使用杠杠的-The experimental class of 16-bit full adder, suitable for beginners, on the use of a lever! ! !
carryskip16
- 16-bit carry skip adder
example7--21.10.2011
- full adder subtractor 16 bit for vhdl
The-VHDL-various-basic-code
- VHDL的各种基本代码 包括4选1,8选1多路选择器，8位全加器，加1减1计数器，序列检测器，异步清零16位加减可控计数器，数码管扫描程序，双2选1，状态机等基本程序！-VHDL basic code including 4 election 1,8 to 1 multiplexer selector, 8-bit full adder, plus 1 minus 1 counter sequence detector, asynchronous clear 16 plus or minus
Vhdl-Implementation-of--Fast-32x32-Multiplier-Bas
- The Vedic mathematics is quite different from conventional method of multiplication like adder and shifter. This mathematics is mainly based on sixteen principles. The multiplier (referred henceforth as Vedic multiplier) architecture base
ADDER16B
- 16位加法器,用于计算比较大的数据，希望对大家有帮助，多点下载，非常感-sixty bit adder
16bit-ALU
- 16位ALU。包括超前进位加减法器、大小比较、算术逻辑位移等运算-16-bit ALU. Including lookahead adder-subtractor, size comparison, arithmetic and logic operations displacement
EDA
- 1.八进制计数器 2.八位右移寄存器 3.八位右移寄存器（并行输入串行输出） 4.半加 5.半加器 6.半减器 7.两数比较器 8.三数比较器 9.D触发器 10.T触发器 11.JK1触发器 12.JK触发器 13.三位全加器 14.SR触发器 15.T1触发器 16.三太门 17.有D触发器构成的6位2进制计数器 18.带同步置数的7进制减法计数器（6位右移寄存器） 19.二十四进制双向计数器 20.二选一 21
da2c
- VHDL硬件描述语言实现DA转化-In quurtus call half adder to achieve 16-bit serial adder
mips.tar
- VERILOG CODE FOR 16- bit ripple carry adder
16x16multiplier
- Design, simulate and synthesize a 16-bit integer multiplier using only one 4-bit adder. This 4-bit adder is to be made with four 1-bit adders as components. The coding is in VHDL.-Design, simulate and synthesize a 16-bit integer multiplier using only
VERILOG-Simulation
- This VERILOG simulation example shows a 16 bit group ripple adder circuit for FPGA. The netlabel is used to split 16 bit bus to four 4 bit bus and connect them to four 4 bit adder. The result is joined to a 16 bit bus using netlabel. The Simulation c
alu
- 实现了四位快速加法器，并在此基础上实现了16位和32为快速加法器(Based on the implementation of four bit fast adder, 16 bit and 32-bit fast adders are realized)