搜索资源列表
Multiplier-shifter-design-tradeoffs-in-a-32-bit-m
- excellent paper which is about the design of MIPS Architecture in the field of computer science and technology
Multiplied-by-large-Numbers
- 汇编 大数相乘 include irvine32.inc value3=value1*value2 .data str1 byte "请输入16进制的32位整数(乘数)（8个）：",0 str2 byte "请输入16进制的32位整数(被乘数)（8个）：",0 str3 byte "相乘结果为：",0 value1 dword ? 乘数 value2 dword ? 被乘数 value3 dword 2 dup(0) 结果 m dword 0 用m
CoreFIR_RTL-3.0
- actelIP核 的fircore Core Generator – Executable File Outputs Run-Time Library (RTL) Code and Testbench Based on Input Parameters – Self-Checking – Executable Tests Generated Output against Algorithm • Distributed Arithmetic (DA) Algori
Ex3_4
- 两个16位整数相乘，乘积总是“向左增长”，这意味着多次相乘后乘积将会很快超出定点器件的数据范围。而且要将32位乘积保存到数据存储器，就要开销2个机器周期以及2个字的程序和RAM单元；并且，由于乘法器都是16位相乘，因此很难在后续的递推运算中，将32位乘积作为乘法器的输入。然而，小数相乘，乘积总是“向右增长”，这就使得超出定点器件数据范围的是我们不太感兴趣的部分。在小数乘法下，既可以存储32位乘积，也可以存储高16位乘积，这就允许用较少的资源保存结果，也便于用于递推运算中。这就是为什么定点DSP芯
booooth
- 32 bit boodth multiplier designed using verilog code
ATmega16A
- High-performance, Low-power Atmel AVR 8-bit Microcontroller Advanced RISC Architecture ̶ 131 Powerful Instructions – Most Single-clock Cycle Execution ̶ 32 x 8 General Purpose Working Registers ̶ Fully Static Operation
multiplierstructural16
- this file is vhdl code of structural multiplier 32 bit.
32bitvedic and square
- 32 bit vedic multiplier documentation
FP_multiplier
- Multiplier for 32 bit with test bench using verilog HDL