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FPGA
- 此课件是基于FPGA的加密芯片设计实例，DES的FPGA实现，包括DES加密算法简述，DES的伪代码描述，设计流程，运算电路模型设计，算法程序设计 -The courseware is based on the FPGA chip design example of encryption, DES for FPGA implementation, including the DES encryption algorithm briefly, DES pseudo-code descr ipt
sbox
- verilog code for s-box generation for AES algorith
AES_enc_core_tb
- this code discribers testbench for aes algorithm. it is written by .vhdl
AESvhdl
- AES vhdl, encryption, decryption code
aes_imp
- AES CODE IN VHDL FOR ENCRYPTION AND DECRYPTION
codeVHDL
- code vhdl for encrypt and dencrypt aes
aes_crypto_core_latest.tar_2
- VHDL CODE FOR AES CRYPTO CORE
aes_pipe
- 流水线AES加密VHDL代码，代码规范，值得参考- The VHDL code of Pipelined AES encryption
aes128-bit
- vhdl code for aes 128 bit
new
- vhdl code aes algorithm newly modified
des_vhdl_code
- decription aes using vhdl code
dec_aes
- decription aes vhdl code for fpga
Project
- 基于FPGA的AES算法的VHDL实现，低内存模式-aes vhdl code
AES-FPGA
- 本文介绍了AES加密算法通过不同的功能结构的FPGA实现，语言背景为VHDL-This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA
aes_thesis_v1.0
- aes code in verilog vhdl language which is very useful.
avs_aes_latest
- This is source code for something very important that is AVS AES standard hardware code for implementation both ASIC and FPGA
Coding Files
- We present an efficient hardware architecture design & implementation of Advanced Encryption Standard AES Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology NIST of United States has been widely