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dds
- 在altera的FPGA上实现直接数字频率合成,即用verilog实现DDS,输出正弦波形,在modelsim软件中仿真通过,已包含所有代码和工程以及二进制流文件。-The realization of direct digital frequency synthesis in the Altera FPGA, which is implemented by Verilog DDS, the output sine wave, through the simulation in Modelsim
dds
- FPGA所需要的DDS源码,可实现波形输出,采用VHDL语言,简单易懂。-FPGA need DDS source waveform output can be achieved using VHDL language, easy to understand.
DDS
- FPGA实现DDS波形发生器,多种信号的产生,-FPGA realization of DDS waveform generator to produce a variety of signals,
DDS
- Verilog HDL实现FPGA的DDS功能,含有实验原理与代码程序-FPGA Verilog HDL realize the DDS function, principles and codes containing experimental procedures
DDS
- 基于fpga的正余弦波形发生器,Verilog代码,测试通过。-Cosine waveform generator fpga based, Verilog code, the test passes.
DDS
- 基于FPGA的DDS波形发生模块,频率相位可调-Module based on FPGA DDS waveform,Adjustable frequency phase
DDS
- 主要现实FPGA中TLV5618模块,学习将模拟电流信号转化为数字信号,并且显示到数码管,本程序范围0-5V-TLV5618 major reality in the FPGA module, learning the analog current signal into a digital signal, and the digital display, the program range 0-5V
DDS-MY-WORK-1
- FPGA模拟数字信号发生器DDS verilog-FPGA analog and digital signal generator DDS verilog
dds
- 使用FPGA产生DDS信号发生器,方便移植,适合新手学习,开发环境Q2-Use FPGA generate DDS signal generator, easy migration, suitable for novices to learn, develop environment Q2
DDS
- 基于FPGA的数字信号合成器(DDS),采用VHDL语言编写,能够实现正弦波、三角波、方波、锯齿波这四种波形的产生。 提示:最后输出的模块是串行DA,可根据具体情况更改驱动。-Digital synthesizer (DDS) based on FPGA, using VHDL language, to achieve sine wave, triangle wave, square wave, sawtooth waveform generation four. Tip: The la
DDS
- 基于FPGA的用VHdl硬件语言实现的直接数字合成(DDS)。-FPGA hardware with VHdl of DDS-based language.
DDS
- DDS的核心是相位累加器,相位累加器有一个累加器和相位寄存器组成,它的作用是再基准时钟源的作用下进行线性累加,当产生溢出时便完成一个周期,即DDS的一个频率周期。加载Matlab 产生的波形,通过FPGA输出DDS信号-Core DDS is the phase accumulator, a phase accumulator and phase accumulator registers, its role is to carry out a linear accumulation under
DDS
- 基于fpga的DDS详细设计方案 verilog语言 正弦计算器则对该相位值计算数字化正弦波幅度(芯片一般通过查表得到)。DDS芯片输出的一般是数字化的正弦波,因此还需经过高速D/A转换器和低通滤波器才能得到一个可用的模拟频率信号。-Direct Digital Synthesizer base on fpga use verilog Sine calculator to calculate the value of the digital phase sine wave amplitu
DDS
- 附件包括1.基于FPGA实现DDS正弦波产生2.对应程设计说明一份3.重要说明一份。使用的软件平台为ISE13.3,硬件平台为Xilinx公司的V4板子。-DDS generator
NCO
- 基于FPGA的DDS设计,通过外接DA转换器输出稳定的正弦波,方波和三角波,可单独产生时钟,不必借助硬件连接,包含寄存器程序,累加器程序和时钟发生电路等,以及顶层设计原理图-The DDS FPGA-based design, through an external DA converter output stable sine wave, square wave and triangular wave, can produce a single clock, without the help
DDS
- 在C8051F360上结合FPGA实现DDS-Combining the FPGA to realize DDS on C8051F360
DDS
- DDS的FPGA实现(VHDL),只可调频,调幅可于外部DA实现。(内附三角波、正弦波、方波的rom调用)-DDS on FPGA (VHDL), only FM, AM can be implemented in an external DA. (With triangular wave, sine wave, square wave rom call)
DDS
- FPGA,ISE12.2,DDS代码,VHDL语言-FPGA, ISE12.2, DDS the code, VHDL language
DDS
- 本代码可以实现基于FPGA的DDS系统设计,实现效果好-This code can be realized based on FPGA DDS system design, implementation effect is good
DDS
- 基于DDS算法的正余弦信号发生器的FPGA实现-Based on DDS Algorithm cosine signal generator FPGA