搜索资源列表
RS232
- DE0 EP3C16F484 RS232串口说明-DE0 EP3C16F484 RS232 DE0 EP3C16F484 RS232 DE0 EP3C16F484 RS232
part1
- LAB 1 - Part 1 DE0 VHDL Tutorial
multifuctional-digital-clock
- 多功能数字钟，万年历，可显示时间，年月日，闹钟，功能十分强大，在DE0上通过-Multifunction digital clock, calendar, you can display the time, date, alarm clock, is very powerful in the DE0 by
clock
- 多功能数字钟，具有调时校时，整点报时，闹铃及其设定等功能，可直接下载到DE0开发板上-verilog clock
Exp1_Part234
- Altera Exp1_Part2,3,4 for DE0
Exp1_Part1
- Altera Exp1_Part1,2,3 for DE0
clock_display
- 自己用verilog语言编写的数字钟程序，能在Alter公司的DE0板上完美运行，能时间计时，日期，闹钟，秒表的功能。 欢迎交流学习。-The digital clock program which developed by verilog language can run at Alter DE0 board, to the time time, date, alarm clock, stopwatch function.
Line_Tracer_VHDL
- Simple Line Tracer Code Using FPGA DE0 Board
pulseoximiter1
- 根据血液对光的吸收程度，通过感光器来收集数据，来测试心跳。 TSL235 感光器，放在手指下面，手指上面用光照，从而收集数据。需要配合配件TSL235 感光器，电路板，电阻。-You are going to interface a TSL235 to the FPGA. The TSL235 is a light-to-frequency converter whose output digital bitstream frequency is directly proportional
vga
- VGA project for DE0-nano
phone
- 用DE0开发板实现电话计费器，基本功能：可设置通话模式，能初始化话费余额，拨动开关可进入通话模式，并根据通话时间和相应通话模式扣除相应的费用。通话过程中能够通过开关切换显示通话时间和话费余额，并可暂停通话。压缩包里有详细的WORD文档的说明，包括波形仿真和DE0的引脚功能介绍。-Implemented by DE0 board telephone billing, basic function: to set the call mode, you can initiate credit bala
DE0_developboard_VGA
- DE0开发板VGA接口显示硬件实现，可显示图片。-DE0 board VGA interface to display hardware, display pictures.
DE0_development_board_cd_data
- 这是DE0开发板的光盘资料，是友晶公司的关于altera公司的Cyclone III开发板。-This is DE0 development board disc material, is friend chip of altera company Cyclone III development board.
DE0-PWM-Led-Drive---simulation
- DE0_PWM_LED_DRİ VE_Sİ MULATİ ON
module-DE0
- verilog code for fpga pattern of letters.
DA904_FPGA
- DAC904的FPGA驱动代码，开发环境是Verilog，quartus。所用试验板为DE0-DAC904 driver code for FPGA development environment is Verilog, quartus. The test plates used to DE0
DDS_FPGA
- 任意波形发生器FPGA实现，Verilog语言编程，试验板为DE0-Arbitrary Waveform Generator FPGA implementation, Verilog language programming, test panels of DE0
Verilog_HDL_FPGA_washing
- 基于Verilog_HDL的FPGA程序(智能洗衣机) 以DE0板为开发工具-The FPGA-based Verilog_HDL program (smart washing machines) for the development of tools to DE0 board
DE2-115 Ephoto
- The 4.3" Ultra-high Resolution LCD Touch Panel Development Kit provides users a 800x480 full-color high-quality LCD Touch Panel with complete reference designs and source code allowing users to develop applications by a touch panel on the Altera
user_first_fpga_20170620
- 程序可实验开发板上LED循环点亮，且可通过按键控制流动速度，用到了PLL IP 和 计数器模块。(Program with LED flashing circuit uses PLL IP and counter. And extinction rate is controled by key.)