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FIFO
- 进程调度算法有FIFO，优先数调度算法，时间片轮转调度算法，分级调度算法，把各种算法用C语言实现-Process scheduling algorithm FIFO, priority number scheduling algorithm, time slice rotation scheduling, hierarchical scheduling algorithm, the various algorithms using C language
fifo
- FIFO 是一种先进先出数据缓存器，这是一个同步FIFO的VHDL源程序，将FIFO分成几个模块进行设计，最后用顶层文件进行模块化设计。-FIFO is a FIFO buffer, which is a synchronous FIFO in VHDL source code, will be divided into several modules FIFO design, top-level files Finally, the modular design.
FIFO
- FIFO设计的难点在于怎样判断FIFO的空/满状态。为了保证数据正确的写入或读出，而不发生益处或读空的状态出现，必须保证FIFO在满的情况下，不能进行写操作。在空的状态下不能进行读操作。怎样判断FIFO的满/空就成了FIFO设计的核心问题。-FIFO design challenge is how to decide the FIFO empty/full. In order to ensure the correct data is written or read, or read the b
FIFO.rar
- 一个操作系统试验 虚拟存储器页面转换FIFO算法模拟实现,An operating system virtual memory page test conversion FIFO algorithm simulation
SCI_FIFO.rar
- F2812 SCI FIFO中断发送和接收例程,F2812 SCI FIFO interrupt routines to send and receive
Verilog_CY7C68013-SLAVE-FIFO
- 用VERILOG 编写 CY7C68013 usb数据采集SLAVE FIFO模式驱动程序 ，已验证过-Prepared with the VERILOG CY7C68013 usb data acquisition SLAVE FIFO mode driver, has proven
FIFO-LFU
- 用C语言实现操作系统请求页面调度算法FIFO LFU的实现 提前装入0，5,6页最后能够计算出缺页中断率-Operating system using C language the page is requested the implementation of scheduling algorithms FIFO LFU advance into 0,5,6 page last page fault rate to calculate the vacancy
fifo_32_4321.rar
- 用verilog写的输出数据宽度可变的FIFO,输入数据为32-bit，输出数据可以配置为4-1任意bit。有设计文件和testbench,Use verilog to write a variable width of the output data FIFO, input data for the 32-bit, output data can be configured as 4-1 arbitrary bit. There are design files and testbench
FIFO
- 基于FPGA的FIFO控制器的设计与实现，ISE，verilog-FPGA-based design and implementation of FIFO controller, ISE, verilog
FIFO64
- FIFO级联，利用verilog语言实现Xilinx FIFO18单元的多个级联，增大FIFO深度。-FIFO cascade, using Verilog Xilinx FIFO18 language to achieve a number of cascade units, increasing the FIFO depth.
FIFO_8_8
- FIFO先进先出队列，一种缓存、或一种管道、设备、接口（Verilog HDL程序,内附说明）-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
FX2_Slave_FIFO
- cy68013的从FIFO方式的通信源代码-cy68013 from the FIFO mode of communication source code
asfifodesign
- 异步fifo设计文档，里面包括详细的verilog设计方案及代码。fifo设计是通信中必然设计的设计-a fifo design with code inside, using verilog language
FIFO-verilog
- 两种异步FIFO设计以及源代码（Verilog）-Two asynchronous FIFO design and source code (Verilog)
FIFO
- 异步FIFO国外经典教程，包含两篇重量级文献 -Asynchronous FIFO foreign classic tutorials, including two heavyweight literature
OV7670
- STM32 驱动 OV7670 摄像头 FIFO
mem_ctrl_latest.tar
- 存储器控制FPGA程序，包括ram，fifo，sdram，flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.
pingpang
- FIFO读写，用使用状态机完成两片FIFO读写，乒乓操作。-FIFO read and write, using the state machine complete with two FIFO read and write, ping-pong operation.
shiyan3niu
- 1.利用FLEX10KE系列（EPM10K100EQC240-1X）的CLOCKBOOST （symbol:CLKLOCK）,设计一个2倍频器，再将该倍频器2分频后输出。 对其进行时序仿真。 2.设计一个数据宽度8bit，深度是16的 同步FIFO(读写用同一时钟)，具有EMPTY、FULL输出标志。 要求FIFO的读写时钟频率为20MHz， 将1－16连续写入FIFO，写满后再将其读出来（读空为止）。 仿真上述逻辑的时序，将仿真
uart_fifo
- avr单片机串口先进先出实例程序，这是个人在实际项目中应用的一个例子，还有是定时器的使用方法-Examples of single-chip FIFO serial avr procedures, which are individual projects in the actual application of an example are also the use of timer