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documentsoffifo
- 介绍FIFO的文章，关于同步FIFO或者异步FIFO-FIFO introduced an article on synchronous or asynchronous FIFO FIFO
rs_decoder_31_19_6.tar
- Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1
FirstIN_FO
- FIFO and can be symthesised by any tools.
simple_spi
- 一个简单的ＳＰＩ ＩＰ核，SPI Core Specifications 可以从说明文档中找到！ The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchron
memory_arithmatic
- The programe is emluator the memory arithmatic---FIFO LRU ...in the operate system.-emluator the memory arithm atic --- FIFO LRU operate ... in the system.
EZWVCcode
- 介绍EZW编解码算法的全部代码，该源代码包含有6个文件： EZW.H － EZW编码器头文件 EZW.C － EZW编码器文件 MATRIX2D.H MATRIX2D.C － 编码器数据结果定义和数据操作 FIFO.H FIFO.C － 扫描方式定义：先入先出原则 LIST.H LIST.C － 零树结构定义和操作 UNEZW.C － EZW解码器 -introduced EZW coding of all the code, the source code incl
vga.niosII.compent.v
- 在cyloneIIFPGA平台下设计完成测试通过的VGA控制器代码。显存留在系统的SDRAM中，用FIFO作为缓冲。-in cyloneIIFPGA platform design is completed tests through the VGA controller code. RAM in the system SDRAM, and use as a FIFO buffer.
os8_2_fifo_ST_Blinky
- ucos_ii在str710f2z6上的移植及串口驱动（包含了fifo）源代码。其中“读我。txt”文件中有移植时做的简单笔记。希望对需要的初学者有所帮助。-ucos_ii str710f2z6 in the transplant and Serial Driver (including the fifo) source code. Which "I read. Txt "file a transplant when so simple notebook. Hope to b
verilog.HDL.examples
- 许多非常有用的 Verilog 实例: ADC, FIFO, ADDER, MULTIPLIER 等-many very useful Verilog examples : ADC, FIFO, ADDER, MULTIPLIER etc.
interfaces_for_mixed_timing_systems
- This paper presents several low-latency mixed-timing FIFO (first-in–first-out) interfaces designs that interface systems on a chip working at different speeds. The connected systems can be either synchronous or asynchronous. The designs are the
OS_Scheduler
- 操作系统中进程调度过程的模拟程序，采用的是FIFO算法-operating system process scheduling process simulation program, using the FIFO algorithm
VHDL.fifo
- 在网上找到的通用存储器vhdl代码库，觉得挺好用的。-the Internet to find the common memory vhdl code library, feeling very good use.
hardwarefifo
- Development tools and sources fifo.c-Development tools and sources fifo.c
cache4j_0.4_src
- cache4j是一个有简单API与实现快速的Java对象缓存。它的特性包括：在内存中进行缓存，设计用于多线程环境，两种实现：同步与阻塞，多种缓存清除策略：LFU, LRU, FIFO，可使用强引用(strong reference)与软引用(soft reference)存储对象。-cache4j is a simple API and achieving rapid Java Object Cache. Its features include : in memory for caching,
!061210[1].pdf
- 基于FPGA的异步FIFO的软硬件实现,通过VERILOG编程实现后下载到FPGA芯片
fifo1.pdf
- 提出了利用fifo,实现dsp之间的高速、实时、可靠的数据传输,介绍了fifo原理及性能特点，详细阐述了系统的硬 件接口电路及软件设计。 -the use fifo achieve dsp between the high-speed, real-time, reliable data transmission, fifo on the principles and performance characteristics of a detailed descr iption of the
fifo2.pdf
- 以TI公司的DSP芯片TMS32OC6204为例，结合IDT公司的先进先出缓存芯片IDT72V3640，介绍了其扩展总线XB在DMA控制下对FIFO进行读写，以实现对图像的实时采集、处理。 -to TI's DSP TMS32OC6204 example, The combined company IDT FIFO-chip cache IDT72V3640. on the expansion of the bus XB under the control of DMA FIFO r
fifo3.pdf
- 重点介绍了DSP与FIFO的数据传输、DSP与USB的接口电路。解决了一般情况下系统无法做到的用线阵CCD实现二维图像信号复原的问题 -focus on the DSP and FIFO data transmission, DSP and USB interface circuit. Solve the system under normal circumstances can not do in line with two-dimensional CCD image signals of
FIFO_BEFORE
- 是基于fpga的FIFO乒乓操作，后面是与SDRAM接口的，这样主要方便sdram的刷新-fpga is based on the FIFO Table Tennis operation, and is behind SDRAM interface, This major update to the convenience sdram
MYMM1
- M/M/1单服务台排队系统仿真（用事件调度法实现离散事件系统仿真） 顾客到达模到达时间间隔和顾客服务时间均服从负指数分布，单服务台系统，按照单队排队，按FIFO方式服务。考察服务n个顾客（n=1000，2000，3000，5000）后的顾客平均队长及平均排队等待时间。-M/M/1 single-server queuing system simulation (using Event Scheduling Method Discrete Event Simulation System) t