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eda
- 利用vhdl设计fir滤波器，有完整程序， 包含加法器，乘法器。-Design using vhdl fir filter, a complete program, including adders, multipliers.
filter1
- 题为基于CSD编码的FIR数字滤波器设计.该滤波器具有线性相位,系数减半.采用VHDL语言编写.是我们EDA课程的作业,得了优.希望对大家有用-Entitled based on CSD code FIR digital filter design. That the filters have linear phase, coefficient half. Using VHDL language. Is the EDA program operations, got excellent. Hop
21840263filter-vhdl-code
- 这是我看到的一个关于FIR滤波器的资料，和大家分享。-This is what I see about FIR filter information to share with you.
filtref
- fir vhdl programme altera
FPGAdesignandFIRimplementation
- 文档中含有DDS的VHDL实现，FIR滤波器串并FPGA实现，synplify,ISE,ModelSim后仿真流程和FPGA设计的资料-document contains DDS implementation with VHDL , FIR filter serial to parallel and FPGA implementation, and synplify, ISE, ModelSim simulation and FPGA design
20FIRfilterwithCSD
- 20阶FIR滤波器，用CSD编码对参数进行了设计-20-order FIR filter with CSD coding of the design parameters
VHDL
- 滤波器 VHDL 应用VHDL基于FPGA设计FIR滤波器-Application of VHDL-based FPGA VHDL filter FIR filter design
fir_PGA
- 一种基于verilog的fir滤波源码，并带matlab仿真源程序。-Based on the fir filter verilog source code and source code with matlab simulation.
dilbalu_fir7
- basic fir filtering in verilog fpga in vhdl
fir6dlms
- lms算法，自适应滤波器中使用fir滤波器对信号的码间干扰进行均衡-lms
fir
- vhdl code for fir filter
fir
- this file contain a descr iption in vhdl of a fir it contain three part well described to similate the behavior of the this type of filter
FIR_CODE
- 4-taps FIR VHDL code with testbench
VHDL_TipsTricks
- tips to design fir filter step by step
34105908-Multipliers-Using-Vhdl
- ABSTRACT: Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and
FIR_IP_lowpass
- 8阶FIR_IP的VHDL代码以及QuartusII的顶层文件-FIR_IP the VHDL code of order 8 and the top-level file QuartusII
fir(1)
- 基于fpga的fir数字滤波器的设计的用QUARTUS II 做的VHDL语言的源代码-The fir fpga based design of digital filters QUARTUS II to do with the source code for VHDL,
FIR
- 采用vhdl语言 设计FIR滤波器，经调试好使，献给广大硬件开发的朋友参考学习-FIR filter design using vhdl language, so that upon commissioning, the development of friends dedicated to the general hardware reference learning
Digital-Signal-Processing-with-FPGA
- FPGA结合DSP设计，如FIR、IIR滤波器，CORDIC算法,多重采样率信号处理，FFT,有对应的VHDL/Verilog 代码code-FPGA Combines with DSP, FIR 、IIR Digital Filters,CORDIC,FFT,Adaptive Filters，VHDL/Verilog code
FIR-LOOP-
- 数字接收机中的FIR滤波器，环形滤波器设计参考,VHDL代码-the FIR filter， loop filter design in a digital receiver,vhdl code