搜索资源列表
dds_project_FPGA_VHDL
- 基于ＦＰＧＡ的ＤＤＳ波形发生器，ＶＨＤＬ，ＥＰ２Ｃ８Ｑ208Ｃ8Ｎ-DDS waveform generator based on FPGA, VHDL, EP2C8Q208C8N
dds1
- 用ALTERA 公司的fpga芯片，编程语言是VerilogHDL,实现DDS数字信号发生器，可以产生正弦信号，三角信号，矩形信号。-ALTERA company fpga chip, programming languages, Verilog HDL, to achieve the DDS digital signal generator, can generate sine signal, triangle signal, rectangular signal
FANGZHENDAIMA-
- 是用matlabK联合FPGA一起实现波形仿真，不同于大家常见的别的方法。是平行于SILK技术的一种技术-DDS MATLAB 仿真
verilog_dds
- verilog实现dds，用于FPGA产生正弦波，适用于Cyclone 2系列-verilog achieve dds, FPGA is used to generate the sine wave, in the Cyclone Series
DDS_AM
- 基于DDS实现AM信号的调制及解调方案的研究，用于FPGA设计中。-The AM signal modulation and demodulation scheme based on DDS for FPGA design.
dds_project
- DDS直接数字频率合成器，能产生正弦波，方波，锯齿波，三角波四种波形，同时能在12864上显示波形类型和频率，用FPGA verilog实现的-DDS direct digital frequency synthesizer can produce sine, square wave, sawtooth wave, triangle wave four waveform, while in the 12864 on display the waveform type and frequency
5-15
- DDS的实现，在XILINX的FPGA验证通过。使用ROM实现的。-DDS implementations, in XILINX FPGA verification by. Using ROM.
DDSFPGA
- 在fpga中实现的DDS程序，程序，测试可用-DDS program, implemented in fpga program, the test can be used
DDS_FPGA_Materals
- DDS的FPGA设计原理、结构和原代理，包含源代码和ModelSim仿真，是DDS初学者参考的优秀教程，图文并茂，上手容易！-DDS FPGA design principles, the structure and the original agent, including source code and ModelSim simulation，it is an excellent book for greenhand in studying DDS, the book is composed
dds_double_new
- FPGA用verilog语言编写的 dds程序，两路输出，频率可调，相位可调，输出波形可调-FPGA using verilog language dds program, two outputs, adjustable frequency, phase adjustable, adjustable output waveform
xinhaoyuan
- DDS产生多种波形信号发生器，包括正弦波，三角波，方波，锯齿波。运行于Altera Cyclone FPGA平台。-DDS signal generator generates a variety of waveforms including sine, triangle wave, square wave, sawtooth wave. Running on Altera Cyclone FPGA platform.
2fsk_0516
- 运行于Altera Cyclone FPGA平台,基于DDS原理的FSK信号发生器，可产生FSK信号-Running on Altera Cyclone FPGA platform, based on the principle of DDS FSK signal generator for FSK signal
sss
- 使用Verilog语言编写源代码.调用一些基本的IP核，如DCM模块、DDS模块ChipScope模块、乘法器模块等来实现调制.最后通过编程并利用FPGA板子实现AM、DBS、SSB的调制。-Using Verilog language source code. Invoke some basic IP cores, such as DCM module, DDS module ChipScope modules, multiplier module to achieve modulation.
mydds
- 通过VHDL编程，在FPGA内实现DDS模块生成正弦波-Through VHDL programming, within the FPGA to realize DDS module to generate sine wave
QAM_verilog
- 基于FPGA的16QAM，用verilog编写，其中DDS为自己编写，含设计文件和testbench。已通过moldesim软件仿真。 -FPGA-based 16QAM, with verilog writing, including DDS for their preparation, including design files and testbench. Simulation software has been through moldesim.
saopin_saveV2
- 在FPGA中利用DDS的原理实现了扫频功能并使用高速的AD采集数据，同时完成了数字峰值检波，并配合高速DA实现数据的输出-Use DDS principle in the FPGA to achieve the sweep function and use of high-speed data acquisition AD, while the completion of the digital peak detection, and with high-speed data output DA
DDS_hzh
- 基于FPGA实现的DDS信号发生器，能产生正弦波、方波、锯齿波三种波形。-FPGA-based realization of DDS signal generator can produce sine, square, ramp three waveforms.
dds_clk
- FPGA工作时钟位50MHz，通过引出FPGA时钟信号，供给外部DDS模块使用。-FPGA clock work bit 50MHz, led by FPGA clock signal supplied to the external DDS module.
cic
- 无线通信中的DDS原理，讲解了FPGA实现数字频率合成器-Wireless communication in the DDS principle, to explain the FPGA to achieve digital frequency synthesizer
FPGA_phase_lock_demodulation
- FPGA 用Verilog语言实现数字锁相解调系统，包含了正交的DDS函数发生器和相应的AD驱动-FPGA digital demodulation system in Verilog lock, comprising a DDS orthogonal function generator and driving the corresponding AD