搜索资源列表
FPGA--DDS-PhaseMeasure
- Verilog实现的DDS正弦信号发生器和测频测相模块,DDS模块可产生两路频率和相位差均可预置调整的值正弦波,频率范围为20Hz-5MHz,相位范围为0°-359°,测量的数据通过引脚传输给单片机,单片机进行计算和显示。
DDS-2
- 用FPGA实现DDS的原理图,结构清晰,采用总线方式与外部单片机通信
用FPGA实现DDS信号发生及用MODELSIM仿真
- 该工程是用verilog编写,FPGA内部产生ROM及ADD加法器。ROM中存正弦波信号。文件夹中还包含modelsim仿真。
DDS.rar
- 自己在Quartus下用VHDL编写的一个DDS程序。包括寄存器,累加器,波形存储器,In Quartus using VHDL procedures for the preparation of a DDS. Including the register, accumulator, waveform memory
DDS.rar
- FPGA控制AD9854的源文件,verilog,附有简单文档。,FPGA to control the AD9854 source file, verilog, with a simple document.
DDS-STC89C52-DAC0800-FPGA.doc
- 电子设计大赛,波形发生器,基于单片机和FPGA的DDS信号源。-Electronic Design Contest, waveform generator, microcontroller and FPGA-based DDS signal source.
DDS
- 基于DDS原理的正弦信号发生器。用VERILOG语言实现,功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
FPGA-DDS
- 在FPGA内,以查表方式实现频率直接合成器(DDS)功能。verilog源代码-In the FPGA in order to achieve the look-up table means the direct synthesizer frequency (DDS) feature. verilog source code
fpga-fpdpsk
- FSK/PSK调制顶层文件 ,正弦波模块 ,正弦波模块初始化文件 ,振幅调整及波形选择模块 ,频率显示值地址产生模块 ,频率步进键核心模块 ,弹跳消除电路-FSK/PSK modulation top-level documents, sine-wave modules, module initialization file sine wave, amplitude adjustment and waveform selection module, the freque
fpga-dds
- 本文介绍了dds的原理以及altera公司的fpga器件FLEX10K系列的主要特点,给出了用EPF10K40实现直接数字频率合成器的工作原理、设计思路、电路结构和仿真结果以及功能改进。-This article describes the principles dds and altera fpga device company FLEX10K series of key features, is given with EPF10K40 the direct digital frequency
DDS
- 利用FPGA的资源实现任意波形的产生,再若和单片机配合就能做成任意的波形发生器。-Use of FPGA resources for the realization of arbitrary waveform generation, again if and SCM can be made with the arbitrary waveform generator.
DDS
- DDS原理介绍,里面是有时序图和系统设计!-DDS principle that there is a timing diagram and system design!
fpga
- 大唐公司的内部学习教程,很好的介绍了可编程器件的学习经验-Datang company s internal learning curricula, introduced a very good learning experience programmable devices
DDS
- 毕业设计,基于FPGA的DDS设计与实现模块-FPGA DDS
DDS
- 基于FPGA的DDS直接信号合成器,基于Altera CYcloneII系列-DDS direct FPGA-based signal synthesis, based on Altera CYcloneII Series
DDS-in-Verilog
- Verilog编写基于FPGA的DDS实现,内含源代码,希望对大家有所帮助。-DDS in Verilog FPGA-based implementation, including source code, we want to help.
DDS
- 基于FPGA的DDS正弦信号设计,文件中有源代码(Design of DDS based on FPGA)
DDS
- 用verilog语言,在fpga上实现dds信号发生器,并在vga上显示出来(Verilog realizes DDS Signal Generator)
DDS
- 基于FPGA的DDS信号发生器,可产生频率可调的正弦波(DDS signal generator based on FPGA)
Signal
- 基于FPGA的DDS相位累加器,连接至存有波形数据的rom后再接至DA可以输出对应的波形(abcdefghijklmnopqrstuvwxyz)