搜索资源列表
DA_TLC56201
- 基于FPGA芯片,应用verilog hdl语言编写DA_TLC5620芯片,实现相应功能的源程序。-FPGA-based application Verilog HDL language DA_TLC5620 chip, the corresponding function of the source.
can_exm1_sys
- CAN总线的数据采集,FPGA到USB。verilog hdl语言。-CAN bus data acquisition, FPGA to the USB. verilog hdl language.
Verilog_HDl
- Verilog HDL是一种硬件描述语言(HDL:Hardware Discr iption Language),是一种以文本形式来描述数字系统硬件的结构和行为的语言,用它可以表示逻辑电路图、逻辑表达式,还可以表示数字逻辑系统所完成的逻辑功能。 -VHDL language is a high-level language for circuit design, digital systems primarily used to describe the structure, behavior,
11223
- 通过使用EDA工具,设计实现简易音乐播放器。在结合各个数字功能模块并利用FPGA系统本身丰富的物理资源的同时,将音乐的乐谱设计在FPGA内部,在Quartus II环境下,采用Verilog HDL 语言实现音乐合成器和播放系统。-By using EDA tools, design and implementation simple music player. The integration of the various functional modules and the use of F
UART_FPGA_Code
- UART FPGA实现过程文档说明,及VERILOG HDL 代码,希望能帮助有需要的人,-UART FPGA implementation process documentation, and VERILOG HDL code, hoping to help people in need, thank you
UART
- FPGA实现串口的收发,可以改波特率。Verilog HDL语言-FPGA Verilog HDL
seg7
- fpga上nios处理器avalon总线数码管驱动,包含任务逻辑,寄存器,和接口的verilog HDL描述-fpga nios processor avalon bus on digital tube driver, including the task logic, registers, and interfaces verilog HDL descr iption
time
- 基于Verilog HDL FPGA开发,时序篇详细教程代码,丰富实例源代码,FPGA学习与参考非常好用-Based on Verilog HDL FPGA development, timing articles detailed tutorial code, abundant source code examples, FPGA is very useful learning and reference
keyqudou
- fpga verilog hdl 设计键盘去抖动程序,设计环境quartusii 9.0。仿真绝对通过。-fpga verilog hdl design keyboard to jitter program design environment quartusii 9.0. Simulation absolutely pass.
main
- 采用现场可编程逻辑器件(FPGA)制作,利用EDA软件中的verilog HDL硬件描述语言控制进行控制,然后烧写实现.按键7~1分别用于七个音符的发音(DO,RE,MI,FA,SO,LA,SI),同时LED灯点亮。按键8和9用于控制乐曲的播放,可以选择三个曲子的播放。-Using field-programmable logic device (FPGA) production, the use of EDA software verilog HDL hardware descr iption
dianzhen
- 这是一个基于FPGA开发实验箱的汉字点阵显示的Verilog HDL程序,经过实验调试验证过的 -This is an FPGA-based development of experimental box character dot-matrix display Verilog HDL procedures, through experimental testing verified
alu16
- 16位运算器,用实例化模块链接,是采用Verilog hdl编程,是实现fpga的代码-16-bit arithmetic unit, with links to instantiate module is using Verilog hdl programming, is to achieve the fpga code
sn74181
- 4位运算器采用sn74181,是采用Verilog hdl编程,是实现fpga的代码,实现了其模块的48种功能,-4 operator uses sn74181, is the use of Verilog hdl programming, is to achieve the fpga code, achieved its module 48 kinds of functions,
IIC
- 使用verilog HDL编写IIC代码,通过FPGA读取mpu6050数据,其他IIC器件代码类似-IIC written using verilog HDL code, read mpu6050 data through FPGA, similar to other IIC device code
uart_async
- RS232串口通信代码,采用verilog HDL实现,在quartus上仿真通过并下载到fpga平台功能验证-RS232 CODE
24
- 基于6M晶振FPGA的篮球24秒计时器verilog HDL代码,附testbench-Verilog HDL code for FPGA-based 6M crystal basketball 24 seconds timer, with testbench
kaoshi
- FPGA -计数器,29减法计数器。使用verilog hdl编写格式,cyclone I 系列EP1C3TC144芯片。-FPGA programming using 29 down counter, using verilog hdl written format, cyclone I series EP1C3TC144 chips.
audio_fft_vga
- 代码使用Verilog HDL实现了使用WM8731对音频进行采样,并且使用ALTERA FPGA实现了频谱计算(FFT),在VGA上显示频谱。-Achieved using the Verilog HDL code using WM8731 audio sampling, and use ALTERA FPGA to achieve the calculated spectrum (FFT), shows the spectrum on VGA.
ADV7123_BOARD
- 基于FPGA的摄像头读入,用到nios软核-verilog HDL
DES-and-3DES
- 用FPGA实现的DES和3DES算法,使用开发板DE2-115通过验证-EDS&3DES based on ALTERA-FPGA,realized by Verilog HDL and DE2-115board.