搜索资源列表
uart
- 用vhdl实现的串口通信程序,可以综合并下载到FPGA运行.-Achieved using VHDL serial communication procedures, can be synthesized and downloaded to the FPGA to run.
uartfifo
- FPGA串口代码实现,带串口模块控制程序-Realization of UART in FPGA, with UART module control codes.
uart
- 基于FPGA的uart源代码,异步串行通信,vhdl书写的。-uart codes。write with vhdl.
kp_uart
- This UART and LCD interface C code Tested on Sparton 3 xilinx FPGA.-This is UART and LCD interface C code Tested on Sparton 3 xilinx FPGA.
CPLD_UART
- 基于FPGA CPLD设计与实现UART,一听名字就知道,不用再说了吧,-FPGA CPLD-based Design and Implementation of UART, a name, we know that you do not say any more,
FPGACPLD
- FPGA数字电子系统设计与开发实例导航> 一书的代码,FPGA数字电子系统设计与开发实例导航,用硬件描述语言编写的,I2C,UART,USB,VGA,CAN-BUS,网络等等的书籍配套原代码。。。。使用方法: 1.拷贝到硬盘。 2.用ISE创建项目,分别加入各个代码文件,即可
uart
- 用FPGA实现uart的verilog源码,包含standard framing error, parity control and overrun detection.-The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and ove
Actel_Igloo_nano_UART
- This FPGA project include a simple version of the UART for Actel Igloo nano.
my_uart_top
- 实现的功能如题,就是FPGA里实现从PC接收数据,然后把接收到的数据发回去。使用的是串口UART协议进行收发数据。上位机用的是老得掉牙的串口调试助手-To achieve the functions such as title, that is, to achieve FPGA receives data from the PC, and then receive data back fat. Using a UART serial port protocol to send and recei
xapp341
- verilog uart for spartan 3 fpga, its great
MCU_FPGA_Interface
- msp430单片机用IO口模拟总线时序,与FPGA进行交互的程序,附源代码,verilog,有简单文档。-msp430 I single-chip analog IO bus with timing, with the FPGA interactive process, with the source code, verilog, a simple document.
LC_txmit
- FPGA UART transmit and so on
URAT_VHDL_CODE
- altera公司的fpga源代码,用VHDL编写的uart程序。-altera' s fpga source code, uart program written using VHDL.
uart16550_latest[1].tar
- 开源UART IP核16550,该IP核兼容16550 UART,具有Modem功能,完全可编程的串行接口具有可设置的字符长度、奇偶校验、停止位以及波特率生成器。-Open-source UART IP core 16550, the IP core is compatible with 16550 UART, with Modem function, fully programmable serial interface can be set up with a character lengt
uart
- the uart model is used to design the synthies and beherival model in verilog fpga
UART_Verilog
- Altera FPGA的UART通讯程序-Altera FPGA' s UART communication program
x3cs400_uart
- 基于X3cS400的串口通讯程序,开发环境ISE7.0,使用verilog编写。可以使用串口调试助手在pc机上查看字符。-UART communication program based on X3CS400 FPGA, develop enviroment: ISE7.0,completed by verilog。 The result could be seen on the Uart debug assitant.
FPGA_RS232
- 为增加系统稳定性,减小电路板面积,提出一种基于FPGA的异步串行口IP核设计。该设计使用VHDL硬件描述语言时接收和发送模块在Xilinx ISE环境下设计与仿真。最后在FPGA上嵌入UART IP核实现电路的异步串行通信功能。该IP核具有模块化、兼容性和可配置性,可根据需要实现功能的升级、扩充和裁减。-In order to increase system stability, reduce board space, presents a FPGA-based asynchronous ser
ThedesignofUniversalAsynchronousReceiverTransmitte
- 本课题所设计的UART支持标准的RS.232C传输协议,主要设计有发送模块、接收模块、线路控制与中断仲裁模块、Modem控制模块以及两个独立的数据缓冲区FIFO模块。该模块具有可变的波特率、数据帧长度以及奇偶校验方式,还有多种中断源、中断优先级、较强的抗干扰数据接收能力以及芯片内部自诊断的能力,模块内分开的接收和发送数据缓冲寄存器能实现全双工通信。除此之外最重要的是利用口模块复用技术设计数据缓冲区FIFO,采用两种可选择的数据缓冲模式。这样既可以应用于高速的数据传输环境,也能适合低速的数据传输场
uart1
- RS232(UART)串口传输,通过了FPGA验证功能正确-UART RS232 verilog HDL FPGA xilinx