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MD5-select-prefix
- MD5选择前缀碰撞关键技术研究 HASH，MD5，差分攻击算法，模差分，差分路径，FPGA，GPU，选择前缀碰撞 -The MD5 select prefix collisions key technology research HASH, MD5 differential attack algorithm mode differential differential path, FPGAs, GPU, select the prefix collision
bell
- 利用VHDL语言进行嵌入式设计（FPGA），蜂鸣器程序，生成蜂鸣器模块-Using VHDL language Embedded Design (FPGAs) buzzer program to generate buzzer module
SHA-1ImplementationOnFPGA
- 希算法SHA-1算法广泛地应用于电子商务、商用加密软件等信息安全领域。通过对SHA．1算法的深入 分析，提出了流水线结构的硬件实现方案。通过缩短关键路径，使用片内RAM代替LE寄存器实现流水线中间变量 的数据传递，有效地提高了工作频率和单位SHA-1算法的计算速度。这种硬件结构在Altera系列芯片上的实现性能 是Ahera商用SHA-1算法IP核的3倍以上。-Hash algorithm SHA-1 is used widely in cryptographic applicati
SPIHT-Image-Compression-on-FPGAs
- SPIHT image compression on FPGA
xapp852.zip
- Xilinx Virtex5 for RLDRAM design,Xapp852 (Xilinx Design RLDRAM II Memory Interface for Virtex-5 FPGAs)
xilinx_intc
- Linux source code, Interrupt controller driver for Xilinx Virtex FPGAs
IMAGE-PROCESSING-(2)
- Image processing is the processing and display of images Improving the visual appearance of images to a human observer, including their printing and transmission Preparing images for the measurement of the features and structures which they revea
94153207-FPGA-ImageProcessing
- The image processing algorithms are inherently parallel & are often implemented with long sequences of basic operations. The high performances of image processing algorithms have been achieved by implementing them on FPGAs.
A3P40_ProASIC3
- ProASIC3, the third-generation family of Actel flash FPGAs, offers performance, density, and features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3 devices the advantage of being a secure, low-power, sing
ss-flexible-design-integration
- Build Flexibility into Your Industrial Applications with FPGAs
Digital-VLSI-Systems-Design.pdf
- A Design Manual for Implementation of Projects on FPGAs and ASICs Using Verilog.
RS
- RS编码英文论文Reed-Solomon Decoder Hardware Implemented in FPGAs: A Prospectus -Reed-Solomon Decoder Hardware Implemented in FPGAs: A Prospectus
pulse_gen
- Pulse generator using VHDL for most of FPGAs
CoreFIR_RTL-3.0
- actelIP核 的fircore Core Generator – Executable File Outputs Run-Time Library (RTL) Code and Testbench Based on Input Parameters – Self-Checking – Executable Tests Generated Output against Algorithm • Distributed Arithmetic (DA) Algori
FPGA-implementation-of-CORDIC
- 就目前的趋势来看，对硬件复杂信号处理的了解主要是缺少对硬件信号处理结构的了解。虽然有许多硬件高效算法的存在，但是由于在过去得25年里软件的优势明显，人们对这些法则并不了解。CORDIC法则就是其中的一个，它是运用平移-相加完成某些三角函数，双曲线，线性，对数的运算功能。虽然有很多的文章已经介绍了CORDIC 运算法则的各种不同的方面 ，却很少有针对CORDIC在FPGA上执行的研究。这篇论文就是研究在一个CORDIC体系下，以往的那些功能是如何完成的，以及解释运算法则如何工作,而且探究针对FPG
SPI-Core_nguyen
- SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE
DBounce
- Using mechanical switches for a user interface is a ubiquitous practice. However, when these switches are actuated, the contacts often rebound, or bounce, off one another before settling into a stable state. Several methods exist to deal with this te
Asynchronous_FIFO
- 异步FIFO代码，虽然是一个比较简单的程序，但有助于我们更好的理解异步FIFO-This implementation is based on the article Asynchronous FIFO in Virtex-II FPGAs writen by Peter Alfke. This TechXclusive Xilinx website. It has some minor modifications.
xapp514
- Audio/Video Connectivity Solutions for Virtex-IIPro and Virtex-4 FPGAs xapp514_latest.之前网站上有一个，但是不是最新的，缺少一些程序，比如xapp514_asrc.zip。这个是最新的版本。-xapp514 Audio/Video Connectivity Solutions for Virtex-IIPro and Virtex-4 FPGAs
FFT-Using-FPGAs-(2)
- FPGA IMPLEMENTATION OF FPGA