搜索资源列表
FPGAprogram2
- 半整数分频器电路的VHDL源程序，供大家学习和讨论。 -half-integer frequency divider circuit VHDL source code for all learning and discussion.
Hkbus16
- 多数位分频器.............................................可直接编译-Contents Paragraphs Page majority-Frequency Divider can be directly translated .......................
compDIVIDER
- 基于VHDL语言描述的一个分频器，根据端口值，可作为四分频，八分频等分频器使用。-based on VHDL descr iption of a divider, according to port value, as a quarter of frequency, Frequency Divider interval such use.
EWB
- EWB做的多功能数字钟 由振荡器输出稳定的高频脉冲信号作为时间基准，经分频器输出标准的秒脉冲，秒计数器满60向分计数器进位，分计数器满60向小时计数器进位，小时计数器按“12翻1”规律计数，计数器经译码器送到显示器；计数出现误差可用校时电路进行校时、校分、校秒， 可发挥部分：使闹钟具有可整点报时与定时闹钟的功能。 -EWB done by the multi-function digital clock oscillator output stable high frequency
feizhenshu
- 非整数分频器 分频系数为无限不循环小数 vhdl-non-integer frequency divider coefficient of circulator is not unlimited vhdl
Verilog_FPGA_fp
- 用Verilog实现基于FPGA的通用分频器-using Verilog FPGA-based Universal Frequency Divider
VerilogHDLshejifengpingqihe32weijishuqi
- 本文件介绍的是用VerilogHDL语言设计分频器和32位计数器.-This paper presents the design using Verilog HDL language Frequency Divider and 32 counters.
divider3
- 一个3分频器。可进一步改装成实际需要的分频器使用-a divider. Can be further converted into actual use of the Frequency Divider
half_clk
- 用verilog编写适中分频器 并且还有测试程序-verilog prepared with moderate frequency divider and another test procedures
fdivision
- 用verilog编写适中分频器 并且还有测试程序-verilog prepared with moderate frequency divider and another test procedures
VHDLEXAMPLEppt
- 介绍8位加法器、分频电路、数字秒表的PPT，带源码，解释详细，一步一步学习，是学习VHDL的好-introduced eight Adder, the frequency divider circuit, digital stopwatch, the PPT, with the source code, explained in detail, step by step, learning, VHDL is a good learning Eastern
fenpinqi
- 《分频器设计》绝对好用的EDA实验程序！已经通过测试。VHDL语言编写-"Frequency Divider" absolutely good for EDA experimental procedure! Already passed the test. VHDL language
cpld
- 一个好用的整数分频电路 保证你喜欢 能够实现对任意整数的分频电路设计-a handy integer frequency divider circuit assures you like to be able to achieve arbitrary integer frequency circuit design
divider
- 用VHDL编写的多次分频器，带有VHDL测试平台代码-Multiple frequency divider with VHDL testbench code
frequency-divider
- 用VERILOG 语言写的数控分频器，可能输入时钟信号实现任意整数倍的分频，-NC divider, with the words written in VERILOG HDL, can achieve any integer multiple of the input clock frequency, contains the entire project file.
Divider
- VHDL代码实现分频器设计 分频器系统时钟20万分频 上升沿触发-VHDL code Divider Design The system clock frequency divider 20 extremely Rising edge triggered
frequency-demultiplier
- 电子分频器：有源电路，位于功率放大器之前，将前置音频信号分频后再用各自独立的功率放大器，把每一个音频频段信号给予放大，然后分别送到相应的扬声器单元-Electronic frequency divider: active circuits, in front of the power amplifier, will lead audio signal frequency and then separate the power amplifier, the every audio frequenc
divider
- 分频器。可实现任意整数分频。占空比为50％，带复位端。-Frequency divider Arbitrary integer frequency can be achieved. Duty cycle is 50 , with reset terminal.
frequency-generation
- 基于VHDL语言的分频器，输入四位比特控制产生相应的输出频率。-Frequency divider based on VHDL language, input control four bits to produce the corresponding output frequency.
Divider
- 用Verilog HDL语言实现分频器，初学，简单(The realization of frequency divider in Verilog HDL, Elementary learning is simple)