搜索资源列表
002
- VHDL语言 用计数器实现分频 N频分频器-VHDL language divide by N counter frequency divider to achieve
SingleLoopSDM_prj
- 对频率综合器中的小数分频器进行优化配置,减小参考杂散。-Of the fractional frequency divider in the synthesizer to optimize the configuration, reducing the reference spur.
frequency5x2
- frequency5x2实现频率的分频,5*2即实现10分频,主要用于满足有些控制类的频率时钟。-frequency5x2 realize the frequency divider, 5* 2 frequency of achieving 10 points, mainly used to control the class to meet some of the frequency of the clock.
5fenpin
- vhdl的时钟信号分频 5分频电路代码 将任意频率5分频-vhdl clock signal frequency divider circuit 5 code any frequency band 5
freqdivider
- Frequency divider application for Verilog programming
DIV_5
- 该源码包包含一个奇分频分频器的Verilog代码及其测试代码。奇分频在许多分频电路中都会用到。-The source code package contains a surprising frequency divider in Verilog code and test code. Odd number of points in the frequency divider circuit will be used in.
yanshichengxu
- 只用单片机实现20Mhz不现实,但可以把频率信号分频,比附超过100K之后就给他2分频,随着频率增加,分频值增加,分频电路需另加硬件,然后分档,分档后的频率测量程序可以用下面的方法测量.- 20Mhz MCU only unrealistic, but the frequency of the signal frequency, after the analogy gave him more than 100K divided by 2, as the frequency increases
PLL_12MHz
- 用verilog语言制作一个PLL,这个PLL可以将频率除频到12MHZ,将PLL除频成12MHZ输出-Verilog language production with a PLL, the PLL frequency divider can be to 12MHZ, 12MHZ into the PLL output divider
cunchuqishuaxin
- 将信号波形数据存放在EEROM中,通过74LS393分频产生不同频率的刷新信号,输出存储器的数据,由DA输出,产生不同频率的信号。. -The signal waveform data stored in EEROM, through the 74LS393 frequency divider to produce different frequency refresh signal, output of memory data, output by the DA, generate sig
Frequency-counter
- 基于FPGA的数字频率计:1. 测量1Hz~1GHz方波的频率,精度为十分位。 2. 档位自动调整,分为1Hz~999.9Hz,1KHz~999.9KHz,1MHz~999.9MHz三个档位。 3. 实现16位的除法器,进行频率的计算,并以ASIIC码输出测量的数据。 -FPGA-based digital frequency meter: 1. Measurement 1Hz ~ 1GHz square wave frequency, accuracy decile. (2)
fenpin_m
- 基于VHDL的一种小数分频器,能够实现任意的小数分频-A decimal frequency divider base on VHDL, be able to achieve any decimal frequency divider
pinglvji
- 硬件电路主要分为信号转换电路、分频电路、数据选择电路、单片机系统和显示电路五部分。 电平转换电路: 电平转换电路的必要性:因为在单片机计数中只能对脉冲波进行计数,而实际中需要测量的频率的信号是多种多样的,有脉冲波,还有可能有正弦波、三角波等,所以需要一个电路把待测信号可以进行计数的脉冲波。 通过电平转化电路将正弦输入信号fx整形成同频率方波fo,要将正弦信号转换成方波信号可以用过零比较电路实现。正弦信号通过LM833N与零电平比较,电压大于零的时候输出LM833N的正电源+5V
VHDLBasicExperimentSJTU
- 上海交大几个基础VHDL 实验的代码,包括分频器,计数器,七段计数器,状态机,锁存器等-Shanghai Jiaotong University and a few experiments of basic VHDL code, including the frequency divider, timer, seven segment counter, state machines, latches, etc.
sync_signals
- Double-FF synchronization stage and frequency divider.
frequency-divider
- 基于VHDL语言实现的数控分频器的设计及其仿真-Based on the numerical control language realization VHDL prescaler design and its simulation
clk_div
- 介绍了一种基于FPGA的小数分频器的分频原理及电路设计- decimal frequency divider based on FPGA
div16_dff
- 该项目用D触发器设计了一个基于VHDL的16分频的分频器,其中包括仿真时序图。-Of the project design with D flip-flop frequency divider 16 points based on VHDL, including simulation timing diagram.
div16_tff
- 该工程设计了一个16分频的分频器,电路采用T触发器,已通过仿真。-The engineering design of a 16 frequency divider circuit using T flip-flop, through simulation.
fsk_tz
- vhdl实现FSK调制,本次毕业设计的数据速率 1.2kb/s,要求产生一个1.2kHz的正弦信号,对正弦信号每周期取100个采样点,因此要求产生3个时钟信号:1.2kHz(数据速率)、120kHz(产生1.2kHz正弦信号的输入时钟)、240kHz(产生2.4kHz正弦信号的输入时钟)。基准时钟已由一个外部时钟120MHz提供,要得到前面三种时钟,就需要首先设计一个模50的分频器产生240kHz信号,再设计一个二分频器,生产一个120kHz的信号,然后再前面的基础上再设计一个模100的分频器,
fenpin
- VHDL编写的分频器,占空比为1:1,可以根据需要,修改计数器,完成不同频率的分频-Divider in VHDL, the duty cycle of 1:1, as needed, modify the counter, complete different frequency divider