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dcm25test
- 采用建立IP核的办法，DCM实现25M分频-The establishment of IP nuclear approach, DCM 25M frequency divider
5fenpinqi
- 实现5分频的分频器程序，并且使用仿真文件进行测试通过。-5 frequency divider program, and tested through simulation file.
op_div_5
- VHDL写的奇数次分频电路，占空比为50 .-VHDL to write odd frequency divider circuit, the duty cycle is 50 .
div
- Quartus下VHDL语言编写的常用分频器（2、4、5、8、10、50、100）等，包含模块图。-Frequency divider in common use under Quartus environment,with module block
odd_division
- 实现了时钟奇数（11）分频器，其它奇数分频只要重新计算div1和div2参数就行了。-Realize the clock odd (11) frequency divider, other odd frequency division as long as recount div1 and div2 parameters will do.
int_div
- 任意计数的分频器，实现功能超强；只需改变分频数字而已-frequency divider vhdl
cshiyan2012
- 基于EDA软件平台上，用硬件描述语言verilog设计完成分频器、计数器、串行移位输出器、伪码发生器、QPSK I/Q调制器、QPSK I/Q解调器，基于选项法中频调制器，再将各个模块综合起来组成一个完整系统；并用quartusII软件对其进行仿真验证。-EDA software platform based on the hardware descr iption language verilog design complete shift of the frequency divider,
clkdiv
- 任意分频电路的verilog实现，包含奇分频和偶分频-Arbitrary divider circuit verilog achieve, contains odd and even frequency divider
8253
- 微机实验 1、编写程序：使用8253的计数器0和计数器1实现对输入时钟频率的两级分频，得到一个周期为1秒的方波，用此方波控制蜂鸣器，发出报警信号，也可以将输入脚接到逻辑笔上来检验程序是否正确。 2、使用8253，编写一个时钟程序。 -Microcomputer Experiment 1, the preparation process: 8253 counter 0 and counter two of the input clock frequency divider, a per
Frequency_Div
- it is vhdl code for "frequency divider" which was implemented and run in altera quarts- -it is vhdl code for "frequency divider" which was implemented and run in altera quarts- II
1freqdiv
- 使用VHDL代码高速而有效的实现了频率的分频，整个工程全部上传，bit文件可以直接下载-VHDL code fast and effective frequency divider, the whole project upload all bit file can be downloaded directly
FREQ-DIV-50MHz-to-64kHz
- Frequency divider implement on DE1 board, Clock in (OSC = 50MHz)to 64kHz
fenpindianlu
- 分频电路包括2MHZ5MHZ10MHZ50MHZ100MHZ-The frequency divider circuit comprises 2MHZ5MHZ10MHZ50MHZ100MHZ
clk_div_50
- a kind of frequently used frequency divider as the divider factor is 50 in the code, you can change it as your wish.
odd_div_ok_
- Learning FPGA students can see, this code USES the VHDL language written by an odd number of frequency divider, not only can learn QUARTUS software, also can better enhance the digital circuit design.
UniversalDIV
- UNIVERSAL FREQUENCY DIVIDER pin sets for Digilent Basys 2 (Spartan3E-250) fout = (K(0)*100+ K(1)*10 + K(2))*10K(3)
dpll2
- 数字锁相环的vdhl实现，鉴相器，计数器，压控振荡器，和分频器-Vdhl DPLL implementation, the phase detector, a counter, a voltage controlled oscillator, and a frequency divider
fenpin
- 对主时钟的完成四分频的分频，希望对大家有帮助。-Completion of the master clock frequency divider quarter, we want to help.
divider13
- 这是一个13分频器，可以进输进来的信号进行13分频后输出-This is a 13 frequency divider which can transfer the input clock signal into a 1/13 clock signal.
divider8
- 这是一个8分频器，可以将输进来的信号进行8分频后输出-This is a 8 frequency divider which can transfer the input clock signal into 1/8 clock