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- IEEE STD 754 的格式说明和算法的C语言实现IEEE_754-IEEE STD 754 and the algorithm descr iption format C language IEEE_754
Float_point
- 浮点数加/减法器的设计 规格化的浮点数运算器 IEEE标准754 单精度-Floating-point add/subtract device design normalized floating-point arithmetic unit single-precision IEEE Standard 754
IEEE754_float-type
- 解读IEEE标准754：浮点数表示，及IEEE754标准的转换-Interpretation of IEEE Standard 754: floating-point representations, and the IEEE754 standard conversion
s_frexp
- IEEE 754 logb. Included to pass IEEE test suite. Not recommend. Use ilogb instead.
s_significand
- for exercising the fraction-part(F) IEEE 754-1985 test vector.NDK r8d: Add android_setCpu().
ieee_test
- IEEE functions for satisfying IEEE 754 test.
fpu_double
- The Verilog version of the code is in folder “fpu_double”, and the VHDL version is in folder “double_fpu”. There is a readme file in each folder, and a testbench file to simulate each core. These cores are designed to meet the IEEE 754 standard f
half_float-master
- half_float: C implementation of a 16 bit floating-point type mimicking most of the IEEE 754 behaviour. Compatible with the half data type used as texture format by OpenGl/Direct3D.
SVM
- State vector machine with single class output. The code works on 32 bit numbers in IEEE 754 floating point format for single precision numbers.
VHDL-Samples
- VHDL Samples，8-bit calculator controller；vending machine controller with typical vending machine logic ；mplements (most of) the logic required to implement a IEEE 754 multiplier unit.
floatConvert
- 根据IEEE754规定写了个float型数据与二进制数转换的方法-According to the provisions of the IEEE 754 wrote a float data and binary conversion method
fp_adder_subtractor
- 本文介绍用于计算IEEE 754标准的双精度64位浮点二进制数加/减法硬件架构。-In this article, an optimized pipeline hardware architecture for computing IEEE 754 standard double precision 64-bit floating point binary number addition/subtraction was proposed.
adder
- 能够实现单精度浮点加法运算。输入引脚有：第一运算数，第二运算数，复位信号，时钟信号。输出信号有：运算结果，运算完成标志。(To achieve a single precision floating-point addition operations)
Coding Files
- Floating Point FP multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. A high speed floating point double