搜索资源列表
FLASH
- SST39VF400A的IP核,可直接用于microblaze的应用里,在合众达FEM024直接使用-SST39VF400A the IP core, can be used directly microblaze applications, the direct use in the Triangle over FEM024
SOPCVGAIP3090114
- 基于 SOPC 的 VGA IP 核设计-Based on SOPC the VGA IP core design
fft
- 基于VHDL语言编写的FFT程序,256点,旋转因子存在自己编写的ROM里面,乘法器和数据存储采用的是IP核-FFT-based program written in VHDL, 256 points, there is rotation factor which I have written the ROM, multiplier, and data storage is used in IP core
lcd12864_avalon_interface
- 12864液晶的ip核,niosII,avalon总线。-12864 LCD ip nuclear, niosII, avalon bus.
a8254
- 基于8254 ip 核的vhdl的实现以及对于quart 2的实现及应用-Based on the 8254 IP core of the realization of VHDL and for the implementation and application quart 2
quartusfft
- 文章讲述了quartus中ip核使用,主要是关于fft ip核的使用-the use of ip core in qquartus
test_sdram
- 测试sdram程序,用来驱动sdram ip 核的程序-test sdram
VGA_Controller
- sopc中vga control的ip核,可以直接拿来用,保证正确-sopc vga control of the ip in the nucleus, can be directly used to ensure proper
mac控制器
- mac控制器ip核,语言verilog,开发环境xilinx ise,quartus ii等
Modular_SGDMA_FRAME_BUFFERING
- altera 的sgdma 做的图形液晶 的ip核 可以直接使用
hdlc
- HDLC协议的VHDL源码。接收和发送模块,以及所用FIFO的IP核(Xilinx公司)。-The code of HDLC protocol.Receive and transmit module is contained.
uart2bus
- uart接口到内部总线的IP核,采用VDHL和VERILOG语言编写。-UART interface to Bus IP Core in VHDL and verilog languages
vga_game_demo
- 乒乓球游戏,基于Xilinx板子,并且有vga IP核,使用EDK进行编程-Table Tennis Games
pic10_verilog
- 用verilog实现了PIC10系列单片机的IP核,代码基本来自一篇国外的文章《A Microchip PIC-Compatible RISC CPU IP Core Design and Verilog Implementation》,对一部分进行了改进,主要包括对原文中有一些不可综合的@(posedge clk)语句的改写,使其能通过quartus的编译和综合,并且对跳转部分增加了比较多的注释,这篇文章写得非常好,感谢这篇文章的作者John Gulbrandsen先生,这篇文章让我学到了很多
xapp859_rtl
- xilinx PCIE IP核 包括ddr2 memory interface ML555开发板-xilinx PCIE IP cores containing ddr2 memory interface can be used on ML555 development kit
fuzzyip
- 这是一个我写的关于模糊控制的IP核,简单高效,其中包括寄存器文件等非常全面。-This is a fuzzy control I wrote about the IP core, simple and efficient, including.
DM9000Aethnet
- 国内重点大学使用最广泛的FPGA开发板-DE2板中经常使用的ip核——DM9000A-University of the domestic focus of the most widely used FPGA development board-DE2 board frequently used ip core- DM9000A
SoCWishboneSystem
- SoC-Wishbone System IP核的VHDL语言源代码-SoC-Wishbone System IP core language VHDL source code
CANbus
- 主要是说明can总线协议使用fpga的ip核实现,供使用can总线的人使用-Mainly states can use the FPGA bus protocol of the ip nuclear realized, for people who use the bus can use