搜索资源列表
ip_modelsim
- 对于modesim进行IP核仿真的基础知识-For modesim IP core simulation of the basic knowledge
RAM
- 用verilog实现了IP核的使用,例化了一个RAM,用来进行读写操作,另外还编写了斐波那契数列来进行测试。-Using verilog to achieve the use of IP core, the instantiation of a RAM, used to read and write operations, in addition to the preparation of the Fibonacci sequence for testing.
pic10
- 本文件夹里面的是实现pic10 CPU的全部verilog代码以及相应的测试脚本代码,当然有一些模块是在quartus中直接编辑波形测试的,所以没有响应的测试脚本文件。 tri_state_port的测试还未完成,test_pic10_status_reg.vt和test_pic10_tri_state_port2.vt都没有完成测试任务 其中有三篇文档: PIC10_RISC_Design.pdf:原文(verilog代码基本都来自原文,对一部分进行了改进),这篇文章写
soc_ip-2016-10-12
- 基于ISE14.7,软核SOC的自定义IP核源码,8个寄存器,全部引出,可以作为FL-FS通讯接口,附带几个其他驱动IP核-Based on the ISE14.7, soft-core SOC custom IP core source code, 8 registers, all derived, can be used as FL-FS communication interface, with several other drivers IP core
Buf_FiFo
- verilog 编写的FIFO,里边有IP核和控制模块,-verilog write FIFO, inside the IP core and control module,
ROM
- FPGArom的IP核使用及仿真,Verilog语言,非常详细-IP core and use of simulation FPGArom, Verilog language, very detailed
fft_analyze
- 利用Altera的IP核,实现FFT算法使用信息流模式读写,使用SignalTap II嵌入式逻辑分析仪观察信号,A/D只要是并行的8位芯片都可以。-Achiving FFT by using Altera IP Core,you can observe the signal by the embedded logic analyzer Signal Tap II,as for A/D device, it s suitable for a parllarel 8 bits A/D device
ug479_7Series_DSP48E1
- 该文档详细介绍了XILINX FPGA内部重要的IP核DSP48E的应用方法,官方手册,准确无误-This document describes in detail the XILINX FPGA internal IP core DSP48E application method, the official manual, accurate
CANBus_design
- CAN总线代码,除了opencore上的ip核之外,主要是原创的配置CAN核和数据采集传输部分-CAN bus code, in addition to the ip nuclear opencore on the original configuration of CAN main nuclear data acquisition and transmission section
ROM
- 使用verilog语言实现对altera下cycloneII系列FPGA的片上ROM的创建,读写,调用IP核-Use verilog language to achieve altera under the cycloneII series FPGA on-chip ROM to create, read and write, call IP core
DDR3_SO_DIMM
- 为FPGAddr3的IP核程序,实现ddr3芯片的读写操作-FPGAddr3 for the IP kernel program, the realization of DDR3 chip read and write operations
E4_4_IIR4Functions
- 用verilog语言实现的一个IIR滤波器,因为现在的ise等工具中没有包含相关的ip核,所以需要手动设计。 -With verilog language to achieve an IIR filter, because now ise and other tools do not contain the relevant ip kernel, so the need for manual design.
E4_1_fir1
- 基于ip核的fir滤波器设计,调用了ip核,并实例化,对初学者很有用。-Based on the ip kernel fir filter design, call the ip kernel, and instantiation, very useful for beginners.
dfe_filter
- DEF算法的FIR滤波器verilog代码,内有乘法器IP核,可直接仿真使用-DEF algorithm for FIR filter verilog code with multiplier IP core, can be directly used simulation
Version1_6
- 基于VHDL硬件语言描述的mc8051的IP核,适用于将8051IP核移植到FPGA开发板上的实验,极大的减轻了初学者的工作量- U57FA u4E8EVHDL u786C u4EF6 u8BED u8A0 u63CF u8FF0 u7684mc8051 u7684IP u6838 uFF0C u9002 u7528 u4E8E u5C068051IP u6838 u79FB u690D u5230FPGA u5F00 u53D1 u677F u4
DDS
- 利用ISE中的ip核产生正弦和余弦波形,包含有test测试文件-ISE ip core cosine sine testbench
LCD
- 本实验通过使用 SOPC Builder 搭建一个包含cpu、ram、sdram、pio、lcd定制ip核、jtag _uart”的SOPC系统。 1.通过该系统实现在eclipse的调试串口上显示字符的功能。 2.通过该nios处理器的pio实现流水灯的效果。 3.通过该系统实现在1602液晶上的字符显示。
UART_FIFO
- FPGA,串口调试程序,接收模块,含FIFO IP核-FPGA uFF0C u4E32 u53E3 u8C03 u8BD5 u7A0B u5E8F uFF0C u63A5 u6536 u6A21 u5757 uFF0C u542BFIFO IP u6838
dtysky-FPGA-Imaging-Library-c8cd350
- 一个hls视频库ip libraries,里面包含各种功能的ip核,可进行复用。-A hls video library ip libraries, which contains a variety of functions of the ip core can be reused.
Altera-LVDS_IP
- 自己总结的Altera_LVDS的IP核的设计及仿真分析,已在实际工程中应用到,并且带有源代码和仿真代码,总结的文档,非常有用。(My summary of the Altera_LVDS IP kernel design and simulation analysis, has been applied in practical engineering, and with source code and simulation code, summary of the document, ver