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EP2C8_pll_example.rar
- EP2C8 PLL例化的例子,给不会的人做个参考.专门写的一个.呵呵.不过是Verilog的.,EP2C8 PLL cases of the examples to those who will not be a reference. Specialized write a. Ha ha. But the Verilog.
phase_test
- 基于verilog的鉴相器设计，鉴相器是锁相环的一部分，功能是检测两个时钟是否同步-The phase detector based on verilog design, PLL phase detector is part of function is to test whether the two clock synchronization
ModelSim-for-PLL
- 基于Verilog在的PLL的IP核仿真测试，环境为ModelSim-Verilog-based IP cores in the PLL simulation test environment for ModelSim
PLL
- 用Verilog HDL编写的锁相环程序-Phase-locked loop program written in Verilog HDL
PLL
- PLL锁相环相关Verilog代码，以及时序的操作，相关文件的载入和仿真环境的建立。-The PLL related Verilog code, and the establishment of the timing of the operation, the relevant documents loading and simulation environment.
pll
- 一个基于FPGA的载波同步环的设计，开发语言Verilog，开发工具ISE 14.7，可用于FM接收机中，典型SDR项目-An FPGA-based carrier synchronization loop design, development language Verilog, development tools ISE 14.7, FM receivers can be used, typically SDR project
PLL
- 采用Verilog语言，使用IP核的PLL，产生3种不同频率的输出，已测试验证通过-Using Verilog language, the use of IP cores PLL, produces three kinds of output at different frequencies, it has been verified by test
pll_test
- 描述了利用spartan6系列FPGA，实现PLL锁相环的功能代码(Describes the use of spartan6 series FPGA, PLL PLL to achieve the functional code)
06_pll_test
- 锁相环IP核的使用，包括详细的配置，适合学习使用；(The use of PLL IP core, including detailed configuration, suitable for learning to use;)
pll
- 三相锁相环，应用于电力电子控制，锁相相位角用于3/2变换等(Three phase phase-locked loop is used in power electronic control, phase-locked phase angle is used for 3/2 transformation, etc.)
PLL
- verilog编写的锁相环程序。可以对照参考(Verilog prepared by the phase-locked loop program. Can control reference)
timing_constraints
- 方法能够自动地约束 PLL 的输入和输出时钟。ALTPLL megafunction 中指定的所有 PLL 参数都用于约束 PLL 的输入和输出时钟。(Methods can automatically constrain PLL input and output clock.Named in ALTPLL megafunction.All PLL parameters are used to constrain PLL input and output clocks.)
7f8da115f83d72b263e5818b9374e466
- PLL configuration using FPGA IN VERILOG LANGUAGE FOR BEGINNER
08167129pllverilog
- PLL CONFIGUARTION USING FOAGA IN VERILOG LANGUAGE
17416335PLLfpgapaper
- PLL CONFIGURATION USING FPGA IN VERILOG LANGUAGE
37148515LC
- PLL CONFIGUARTION USING FPGA
at7_ex03
- 使用FPGA内部的PLL产生时钟，计数器循环计数驱动LED闪烁。基于vivado平台编写的Verilog代码(Use FPGA's internal PLL to generate clock, counter cycle counting drive LED flicker. Verilog code based on vivado platform)
PLL
- 本次的设计主要任务是学会调用锁相环 IP 核，并对其进行仿真， 具体要求如下：（1）熟练掌握调用锁相环 IP 核的详细步骤。将 50M 的时钟分成 20MHz 和 100MHz 两个时钟（2）对锁相环进行仿真，验证 调用的锁相环的正确性。(The main task of this design is to learn to call the phase-locked loop IP core.)
sobel
- 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Ve
DPWM
- 用Verilog实现数字脉宽调制模块，主要模块有锁相环、计数器、多路选择器(The digital pulse width modulation module is realized by Verilog. The main modules are PLL, counter and multiplexer)