文件名称:PLL
-
所属分类:
- 标签属性:
- 上传时间:2015-11-17
-
文件大小:3.03mb
-
已下载:0次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
采用Verilog语言,使用IP核的PLL,产生3种不同频率的输出,已测试验证通过-Using Verilog language, the use of IP cores PLL, produces three kinds of output at different frequencies, it has been verified by test
(系统自动生成,下载前可以参看下载内容)
下载文件列表
PLL/
PLL/db/
PLL/db/.cmp.kpt
PLL/db/logic_util_heursitic.dat
PLL/db/my_pll_altpll.v
PLL/db/PLL.(0).cnf.cdb
PLL/db/PLL.(0).cnf.hdb
PLL/db/PLL.(1).cnf.cdb
PLL/db/PLL.(1).cnf.hdb
PLL/db/PLL.(2).cnf.cdb
PLL/db/PLL.(2).cnf.hdb
PLL/db/PLL.(3).cnf.cdb
PLL/db/PLL.(3).cnf.hdb
PLL/db/PLL.(4).cnf.cdb
PLL/db/PLL.(4).cnf.hdb
PLL/db/PLL.(5).cnf.cdb
PLL/db/PLL.(5).cnf.hdb
PLL/db/PLL.(6).cnf.cdb
PLL/db/PLL.(6).cnf.hdb
PLL/db/PLL.(7).cnf.cdb
PLL/db/PLL.(7).cnf.hdb
PLL/db/PLL.(8).cnf.cdb
PLL/db/PLL.(8).cnf.hdb
PLL/db/PLL.(9).cnf.cdb
PLL/db/PLL.(9).cnf.hdb
PLL/db/PLL.asm.qmsg
PLL/db/PLL.asm.rdb
PLL/db/PLL.cbx.xml
PLL/db/PLL.cmp.hdb
PLL/db/PLL.cmp.idb
PLL/db/PLL.cmp.rdb
PLL/db/PLL.cmp_merge.kpt
PLL/db/PLL.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
PLL/db/PLL.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
PLL/db/PLL.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
PLL/db/PLL.db_info
PLL/db/PLL.eda.qmsg
PLL/db/PLL.fit.qmsg
PLL/db/PLL.hier_info
PLL/db/PLL.hif
PLL/db/PLL.ipinfo
PLL/db/PLL.lpc.html
PLL/db/PLL.lpc.rdb
PLL/db/PLL.lpc.txt
PLL/db/PLL.map.ammdb
PLL/db/PLL.map.bpm
PLL/db/PLL.map.cdb
PLL/db/PLL.map.hdb
PLL/db/PLL.map.kpt
PLL/db/PLL.map.logdb
PLL/db/PLL.map.qmsg
PLL/db/PLL.map.rdb
PLL/db/PLL.map_bb.cdb
PLL/db/PLL.map_bb.hdb
PLL/db/PLL.map_bb.logdb
PLL/db/PLL.pplq.rdb
PLL/db/PLL.pre_map.hdb
PLL/db/PLL.pti_db_list.ddb
PLL/db/PLL.root_partition.map.reg_db.cdb
PLL/db/PLL.routing.rdb
PLL/db/PLL.rtlv.hdb
PLL/db/PLL.rtlv_sg.cdb
PLL/db/PLL.rtlv_sg_swap.cdb
PLL/db/PLL.sgdiff.cdb
PLL/db/PLL.sgdiff.hdb
PLL/db/PLL.sld_design_entry.sci
PLL/db/PLL.sld_design_entry_dsc.sci
PLL/db/PLL.smart_action.txt
PLL/db/PLL.sta.qmsg
PLL/db/PLL.sta.rdb
PLL/db/PLL.tiscmp.fastest_slow_1200mv_0c.ddb
PLL/db/PLL.tiscmp.fastest_slow_1200mv_85c.ddb
PLL/db/PLL.tiscmp.fast_1200mv_0c.ddb
PLL/db/PLL.tiscmp.slow_1200mv_0c.ddb
PLL/db/PLL.tiscmp.slow_1200mv_85c.ddb
PLL/db/PLL.tis_db_list.ddb
PLL/db/PLL.vpr.ammdb
PLL/db/prev_cmp_PLL.qmsg
PLL/greybox_tmp/
PLL/greybox_tmp/cbx_args.txt
PLL/incremental_db/
PLL/incremental_db/compiled_partitions/
PLL/incremental_db/compiled_partitions/PLL.db_info
PLL/incremental_db/compiled_partitions/PLL.root_partition.cmp.ammdb
PLL/incremental_db/compiled_partitions/PLL.root_partition.cmp.cdb
PLL/incremental_db/compiled_partitions/PLL.root_partition.cmp.dfp
PLL/incremental_db/compiled_partitions/PLL.root_partition.cmp.hdb
PLL/incremental_db/compiled_partitions/PLL.root_partition.cmp.logdb
PLL/incremental_db/compiled_partitions/PLL.root_partition.cmp.rcfdb
PLL/incremental_db/compiled_partitions/PLL.root_partition.map.cdb
PLL/incremental_db/compiled_partitions/PLL.root_partition.map.dpi
PLL/incremental_db/compiled_partitions/PLL.root_partition.map.hbdb.cdb
PLL/incremental_db/compiled_partitions/PLL.root_partition.map.hbdb.hb_info
PLL/incremental_db/compiled_partitions/PLL.root_partition.map.hbdb.hdb
PLL/incremental_db/compiled_partitions/PLL.root_partition.map.hbdb.sig
PLL/incremental_db/compiled_partitions/PLL.root_partition.map.hdb
PLL/incremental_db/compiled_partitions/PLL.root_partition.map.kpt
PLL/incremental_db/README
PLL/my_pll.ppf
PLL/my_pll.qip
PLL/my_pll.v
PLL/my_pll_bb.v
PLL/my_pll_inst.v
PLL/output_files/
PLL/output_files/greybox_tmp/
PLL/output_files/greybox_tmp/cbx_args.txt
PLL/output_files/my_pll.qip
PLL/output_files/output_files/
PLL/output_files/PLL.asm.rpt
PLL/output_files/PLL.done
PLL/output_files/PLL.eda.rpt
PLL/output_files/PLL.fit.rpt
PLL/output_files/PLL.fit.smsg
PLL/output_files/PLL.fit.summary
PLL/output_files/PLL.flow.rpt
PLL/output_files/PLL.jdi
PLL/output_files/PLL.map.rpt
PLL/output_files/PLL.map.summary
PLL/output_files/PLL.pin
PLL/output_files/PLL.pof
PLL/output_files/PLL.sof
PLL/output_files/PLL.sta.rpt
PLL/output_files/PLL.sta.summary
PLL/PLL.qpf
PLL/PLL.qsf
PLL/PLL.qws
PLL/PLL.vwf
PLL/PLLJ_PLLSPE_INFO.txt
PLL/PLL_nativelink_simulation.rpt
PLL/RTL/
PLL/RTL/greybox_tmp/
PLL/RTL/greybox_tmp/cbx_args.txt
PLL/RTL/my_pll.qip
PLL/RTL/PLL.v
PLL/RTL/PLL.v.bak
PLL/simulation/
PLL/simulation/modelsim/
PLL/simulation/modelsim/greybox_tmp/
PLL/simulation/modelsim/greybox_tmp/cbx_args.txt
PLL/simulation/modelsim/modelsim.ini
PLL/simulation/modelsim/msim_transcript
PLL/simulation/modelsim/my_pll.qip
PLL/simulation/modelsim/PLL.sft
PLL/simulation/modelsim/PLL.vo
PLL/simulation/modelsim/PLL.vt
PLL/simulation/modelsim/PLL.vt.bak
PLL/simulation/modelsim/PLL_8_1200mv_0c_slow.vo
PLL/simulation/modelsim/PLL_8_1200mv_0c_v_slow.sdo
PLL/simulation/modelsim/PLL_8_1200mv_85c_slow.vo
PLL/simulation/modelsim/PLL_8_1200mv_85c_v_slow.sdo
PLL/simulation/modelsim/PLL_min_1200mv_0c_fast.vo
PLL/simulation/modelsim/PLL_min_1200mv_0c_v_fast.sdo
PLL/simulation/modelsim/PLL_modelsim.xrf
PLL/simulation/modelsim/PLL_run_msim_rtl_verilog.do
PLL/simulation/modelsim/PLL_run_msim_rtl_verilog.do.bak
PLL/simulation/modelsim/PLL_run_msim_rtl_verilog.do.bak1
PLL/simulation/modelsim/PLL_run_msim_rtl_verilog.do.bak2
PLL/simulation/modelsim/PLL_run_msim_rtl_verilog.do.bak3
PLL/simulation/modelsim/PLL_run_msim_rtl_verilog.do.bak4
PLL/simulation/modelsim/PLL_run_msim_rtl_verilog.do.bak5
PLL/simulation/modelsim/PLL_run_msim_rtl_verilog.do.bak6
PLL/simulation/mo
PLL/db/
PLL/db/.cmp.kpt
PLL/db/logic_util_heursitic.dat
PLL/db/my_pll_altpll.v
PLL/db/PLL.(0).cnf.cdb
PLL/db/PLL.(0).cnf.hdb
PLL/db/PLL.(1).cnf.cdb
PLL/db/PLL.(1).cnf.hdb
PLL/db/PLL.(2).cnf.cdb
PLL/db/PLL.(2).cnf.hdb
PLL/db/PLL.(3).cnf.cdb
PLL/db/PLL.(3).cnf.hdb
PLL/db/PLL.(4).cnf.cdb
PLL/db/PLL.(4).cnf.hdb
PLL/db/PLL.(5).cnf.cdb
PLL/db/PLL.(5).cnf.hdb
PLL/db/PLL.(6).cnf.cdb
PLL/db/PLL.(6).cnf.hdb
PLL/db/PLL.(7).cnf.cdb
PLL/db/PLL.(7).cnf.hdb
PLL/db/PLL.(8).cnf.cdb
PLL/db/PLL.(8).cnf.hdb
PLL/db/PLL.(9).cnf.cdb
PLL/db/PLL.(9).cnf.hdb
PLL/db/PLL.asm.qmsg
PLL/db/PLL.asm.rdb
PLL/db/PLL.cbx.xml
PLL/db/PLL.cmp.hdb
PLL/db/PLL.cmp.idb
PLL/db/PLL.cmp.rdb
PLL/db/PLL.cmp_merge.kpt
PLL/db/PLL.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
PLL/db/PLL.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
PLL/db/PLL.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
PLL/db/PLL.db_info
PLL/db/PLL.eda.qmsg
PLL/db/PLL.fit.qmsg
PLL/db/PLL.hier_info
PLL/db/PLL.hif
PLL/db/PLL.ipinfo
PLL/db/PLL.lpc.html
PLL/db/PLL.lpc.rdb
PLL/db/PLL.lpc.txt
PLL/db/PLL.map.ammdb
PLL/db/PLL.map.bpm
PLL/db/PLL.map.cdb
PLL/db/PLL.map.hdb
PLL/db/PLL.map.kpt
PLL/db/PLL.map.logdb
PLL/db/PLL.map.qmsg
PLL/db/PLL.map.rdb
PLL/db/PLL.map_bb.cdb
PLL/db/PLL.map_bb.hdb
PLL/db/PLL.map_bb.logdb
PLL/db/PLL.pplq.rdb
PLL/db/PLL.pre_map.hdb
PLL/db/PLL.pti_db_list.ddb
PLL/db/PLL.root_partition.map.reg_db.cdb
PLL/db/PLL.routing.rdb
PLL/db/PLL.rtlv.hdb
PLL/db/PLL.rtlv_sg.cdb
PLL/db/PLL.rtlv_sg_swap.cdb
PLL/db/PLL.sgdiff.cdb
PLL/db/PLL.sgdiff.hdb
PLL/db/PLL.sld_design_entry.sci
PLL/db/PLL.sld_design_entry_dsc.sci
PLL/db/PLL.smart_action.txt
PLL/db/PLL.sta.qmsg
PLL/db/PLL.sta.rdb
PLL/db/PLL.tiscmp.fastest_slow_1200mv_0c.ddb
PLL/db/PLL.tiscmp.fastest_slow_1200mv_85c.ddb
PLL/db/PLL.tiscmp.fast_1200mv_0c.ddb
PLL/db/PLL.tiscmp.slow_1200mv_0c.ddb
PLL/db/PLL.tiscmp.slow_1200mv_85c.ddb
PLL/db/PLL.tis_db_list.ddb
PLL/db/PLL.vpr.ammdb
PLL/db/prev_cmp_PLL.qmsg
PLL/greybox_tmp/
PLL/greybox_tmp/cbx_args.txt
PLL/incremental_db/
PLL/incremental_db/compiled_partitions/
PLL/incremental_db/compiled_partitions/PLL.db_info
PLL/incremental_db/compiled_partitions/PLL.root_partition.cmp.ammdb
PLL/incremental_db/compiled_partitions/PLL.root_partition.cmp.cdb
PLL/incremental_db/compiled_partitions/PLL.root_partition.cmp.dfp
PLL/incremental_db/compiled_partitions/PLL.root_partition.cmp.hdb
PLL/incremental_db/compiled_partitions/PLL.root_partition.cmp.logdb
PLL/incremental_db/compiled_partitions/PLL.root_partition.cmp.rcfdb
PLL/incremental_db/compiled_partitions/PLL.root_partition.map.cdb
PLL/incremental_db/compiled_partitions/PLL.root_partition.map.dpi
PLL/incremental_db/compiled_partitions/PLL.root_partition.map.hbdb.cdb
PLL/incremental_db/compiled_partitions/PLL.root_partition.map.hbdb.hb_info
PLL/incremental_db/compiled_partitions/PLL.root_partition.map.hbdb.hdb
PLL/incremental_db/compiled_partitions/PLL.root_partition.map.hbdb.sig
PLL/incremental_db/compiled_partitions/PLL.root_partition.map.hdb
PLL/incremental_db/compiled_partitions/PLL.root_partition.map.kpt
PLL/incremental_db/README
PLL/my_pll.ppf
PLL/my_pll.qip
PLL/my_pll.v
PLL/my_pll_bb.v
PLL/my_pll_inst.v
PLL/output_files/
PLL/output_files/greybox_tmp/
PLL/output_files/greybox_tmp/cbx_args.txt
PLL/output_files/my_pll.qip
PLL/output_files/output_files/
PLL/output_files/PLL.asm.rpt
PLL/output_files/PLL.done
PLL/output_files/PLL.eda.rpt
PLL/output_files/PLL.fit.rpt
PLL/output_files/PLL.fit.smsg
PLL/output_files/PLL.fit.summary
PLL/output_files/PLL.flow.rpt
PLL/output_files/PLL.jdi
PLL/output_files/PLL.map.rpt
PLL/output_files/PLL.map.summary
PLL/output_files/PLL.pin
PLL/output_files/PLL.pof
PLL/output_files/PLL.sof
PLL/output_files/PLL.sta.rpt
PLL/output_files/PLL.sta.summary
PLL/PLL.qpf
PLL/PLL.qsf
PLL/PLL.qws
PLL/PLL.vwf
PLL/PLLJ_PLLSPE_INFO.txt
PLL/PLL_nativelink_simulation.rpt
PLL/RTL/
PLL/RTL/greybox_tmp/
PLL/RTL/greybox_tmp/cbx_args.txt
PLL/RTL/my_pll.qip
PLL/RTL/PLL.v
PLL/RTL/PLL.v.bak
PLL/simulation/
PLL/simulation/modelsim/
PLL/simulation/modelsim/greybox_tmp/
PLL/simulation/modelsim/greybox_tmp/cbx_args.txt
PLL/simulation/modelsim/modelsim.ini
PLL/simulation/modelsim/msim_transcript
PLL/simulation/modelsim/my_pll.qip
PLL/simulation/modelsim/PLL.sft
PLL/simulation/modelsim/PLL.vo
PLL/simulation/modelsim/PLL.vt
PLL/simulation/modelsim/PLL.vt.bak
PLL/simulation/modelsim/PLL_8_1200mv_0c_slow.vo
PLL/simulation/modelsim/PLL_8_1200mv_0c_v_slow.sdo
PLL/simulation/modelsim/PLL_8_1200mv_85c_slow.vo
PLL/simulation/modelsim/PLL_8_1200mv_85c_v_slow.sdo
PLL/simulation/modelsim/PLL_min_1200mv_0c_fast.vo
PLL/simulation/modelsim/PLL_min_1200mv_0c_v_fast.sdo
PLL/simulation/modelsim/PLL_modelsim.xrf
PLL/simulation/modelsim/PLL_run_msim_rtl_verilog.do
PLL/simulation/modelsim/PLL_run_msim_rtl_verilog.do.bak
PLL/simulation/modelsim/PLL_run_msim_rtl_verilog.do.bak1
PLL/simulation/modelsim/PLL_run_msim_rtl_verilog.do.bak2
PLL/simulation/modelsim/PLL_run_msim_rtl_verilog.do.bak3
PLL/simulation/modelsim/PLL_run_msim_rtl_verilog.do.bak4
PLL/simulation/modelsim/PLL_run_msim_rtl_verilog.do.bak5
PLL/simulation/modelsim/PLL_run_msim_rtl_verilog.do.bak6
PLL/simulation/mo
1999-2046 搜珍网 All Rights Reserved.
本站作为网络服务提供者,仅为网络服务对象提供信息存储空间,仅对用户上载内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。
