搜索资源列表
test_pll
- 使用modelsim se6.5d仿真altpll锁相环 完整工程，verilog代码，因为没找到选的是vhdl-simulation pll with modelsim se6.5d
vga256_success
- Verilog HDL语言编写的256色VGA显示程序，引脚分配适用于21EDA的EP2C8Q208开发板 程序中的PLL分频子模块为我上传的另一代码：PLL_50MHz_to_25MHz.rar-Verilog HDL language, 256-color VGA display program, pin assignment for the 21EDA the EP2C8Q208 development board programs. The PLL frequency sub-mod
VerilogEP2C8Q208PLL_12MHz
- Verilog HDL语言编写EP2C8Q208芯片PLL分频的简单程序 PLL_12MHz-Verilog HDL language EP2C8Q208 chip PLL frequency of the simple program PLL_12MHz
pll_module
- 基于verilog的 FPGA内部PLL模块设计-Based on verilog FPGA PLL design internal modules
m.e-lab
- vhdl verilog code for alu operation pll,biy sliced processor
zl30160_pll_config_interface_model
- zl30160锁相环逻辑配置接口模块,本模块用verilog代码编写，已经过严格的电路板上的实际测试-zl30160 pll configer interface
PLL_12MHz
- 用verilog语言制作一个PLL，这个PLL可以将频率除频到12MHZ，将PLL除频成12MHZ输出-Verilog language production with a PLL, the PLL frequency divider can be to 12MHZ, 12MHZ into the PLL output divider
sdram
- 在ISE环境中，利用verilog语言编写的SDRAM的控制，已经通过功能仿真，其中PLL部分并没有加入，使用时可以自行加入PLL模块。-Verilog language in the ISE environment, the use of SDRAM control, through functional simulation, which the PLL part and did not join, can join the PLL blocks.
timecontrol
- verilog 语言实现巴克码和写串行数据，对PLL进行配置。-using verilog to generate bakema and write series datas for PLL conifgure.
Phase1111_Tracking
- 使用Verilog编写的相位跟踪器，可以有效解决锁相环中的相位跟踪问题，ISE12.2下编译通过-Written in Verilog phase tracker can effectively resolve the PLL phase tracking, ISE12.2 compiled by
Pro_19
- Fpga,DDS,PLL,rom(正弦波)(f<13MHz,需要滤波)(Verilog)-Fpga, DDS, PLL, rom
ex3
- pll ip核结合七段码 verilog源代码-the pll ip core binding seven-segment code verilog source code
ft2232h_rollback
- FT2232H芯片usb循环读写 verilog 实现, 使用时pll可注释掉-FT2232H the chips usb cycle read and write verilog achieve
test_pll_2
- 锁相环的verilog源代码，其中包括发送端，鉴相器，滤波器，压控振荡器的源代码，主要实现输入输出信号的跟踪，捕获和锁定，使输入输出信号在较短时间内达到同步。-This is a verilog code for PLL, including transmitor, PDF, Filter, VCO and so on. It mainly realize the input and output signal tracking, capture and lock, make the in
PLL_success
- 数字锁相环，曼彻斯特的产生与解码,verilog hdl-Digital PLL, Manchester generation and decoding, verilog hdl
pulse_generation
- 一个小的激光驱动电路，调用PLL锁相环，可以产生不同脉宽，实现占空比可调-Pulse generation, Verilog written. Though simple, but I hope you will help
Phase-Locked-Loop
- PLL CODE IN VERILOG DESIGN
frequency
- 时钟信号的各种分频、倍频实现，利用PLL实现及Verilog HDL语言。-The application of different frequency
dpll3
- 数字锁相环 VERILOG语言编写的基于FPGA平台的PLL程序-VERILOG language based on the FPGA platform PLL program
test_verilog---Copie
- a verilog-ams code for a p-a verilog-ams code for a pll