搜索资源列表
frequency
- 用于FPGA开发,使用VERILOG语言编写,并在QUARTUS II仿真平台仿真,实现频率计的功能。(It is used in FPGA development, written in VERILOG language, and simulated on the QUARTUS II simulation platform to realize the function of the frequency meter.)
modified_booth_multiplier
- quartus ii项目文件包,功能是改进的booth乘法器,节省时钟,已完成仿真。(This zip file contains a quartus ii project, which can fufill multiple function. It is done by using a modified booth multiplier.)
AT24C02_IIC
- Quartus II 项目,AT24C02 IIC通信接口,可实现读写功能。(This zip contains an AT24C02 IIC interface, which can read from 24c02 and write data into it.)
lcd5110_耗费资源少
- Quartus II 项目,可驱动LCD5110液晶显示屏。(This zip file contains a quartus ii project, which can driven the LED screen LCD5110.)
通过JTAG固化程序到EPCS的方法
- 在 Quartus II 中,通过JTAG固化程序到EPCS的方法。(The method of JTAG curing program to EPCS.)
quartus ii 9.0 (1)
- 按钮您就能叫你家那叫奶奶看见了就能理解你(buttonjnknjknjnjnkjn)
d974d4330bf7
- 这是一个非常完整的qpsk调制解调用fpga实现的工程,在工程中已经能够正常使用,使用的quartus ii 开发,使用Verilog语言,文件中还包含了各种滤波器的系数文件,还有matlab仿真文件,整个工程包含从串并变换,相位映射,到成型滤波,中通滤波,cic滤波,调制,再到解调过成的下变频,匹配滤波,载波提取,位定时,判决,整个完整的过程(This is a very complete QPSK modulation and demodulation using FPGA implemen
cpu_uart_leds_ip
- 基于Altera 的一个IP核,能完成串口收发,以及自定义IP,可以作为自定义AXI总线接口的例子(Based on Altera's IP core, to complete the serial transceiver, as well as custom IP, as a custom AXI bus interface example)
chuzujifei
- 使用Quartus II 9.0编写的出租车计费系统源码,是课程设计大作业验证通过,可以直接仿真验证(The use of Quartus II 9 written taxis charging system source code, is the course design of large work verification through, can be directly simulated and verified)
crc7
- 以crc7为例进行UVM的验证 Part 1: 搭建环境。 本文使用的Quartus II 13.1(64 bit),器件库MAX V。写了一个Verilog的简单的crc7。 仿真环境是ModelSim 10.2c。虽说自带UVM库。但是,没找到Modelsim自带的uvm_dpi.dll,于是,还重新编译了一番。 本文在win 10下。下载uvm-1.1d(现在最新版本有1.2d了),放好。(crc7 code by system verilog language)
tablet
- Quartus II 13 patch codes
license_quartus
- this is a licence file to crack quartus II version 15
vga_driver
- 使用CycloneIV,驱动800*600*60hz的VGA显示标准,将彩色图片存储在ROM中,最后动态读取到标准液晶显示器里。(Using CycloneIV, it drives the VGA display standard of 800*600*60hz, stores the color pictures in ROM, and finally reads it into the standard liquid crystal display.)
SOPC LED实验
- 通过Quartus II、SOPC Builder、Nios II IDE三种工 具的配合使用 用软件控制led,VHDL程序通过描述硬件电路控制led的依次亮灭(Through the Quartus II, SOPC Builder, Nios II IDE three workers With the use Use software to control led, VHDL program by describing the hardware circuit control l
cnt4M
- 基于Quartus II 的VHDL语言编程实现的一个50M分频器(50M frequency divider)
fft_32k
- FFT 32K点设计实例v1.0.0自述文件 本自述文件包含以下部分: 工具要求 o Quartus II编译 o ModelSim仿真模型 o MATLAB模型(FFT 32K Point Design Example v1.0.0 README File This readme file for the Fast Fourier Transform (FFT) 32K Point Design contains information about the design exam
DE2_115_LCD
- 用FPGA来实现LCD的相关功能,主要用Quartus II 来开发(Using FPGA to achieve LCD related functions, mainly using Quartus II to develop)
实验2
- 在Quartus II环境下,设计含有时钟同步使能的十进制加法器,并下载到实验板上进行验证。(Design a decimal adder with clock synchronization enable)
led
- 流水灯实验,实现四位流水灯功能 本次的设计主要是一个简单流水灯驱动程序,要求流水灯模式 如下:(1)复位时,灯全部熄灭。(2)复位按键放开时,首先点亮 第一个灯,然后第一个 灯熄灭,同时点亮第二个灯;接着,第二个 灯熄灭,同时点亮第三个灯;再然后,第三个灯熄灭,同时点亮第四 个灯;最后,第四个灯熄灭,同时点亮第一个灯;如此循环往复,实 现流水。(Running water lamp experiment to realize the function of four bit flow
PLL
- 本次的设计主要任务是学会调用锁相环 IP 核,并对其进行仿真, 具体要求如下:(1)熟练掌握调用锁相环 IP 核的详细步骤。将 50M 的时钟分成 20MHz 和 100MHz 两个时钟(2)对锁相环进行仿真,验证 调用的锁相环的正确性。(The main task of this design is to learn to call the phase-locked loop IP core.)