搜索资源列表
ask_fsk
- 数字通信系统振幅键控ASK信号和频移键控FSK的调制与解调的VHDL代码-ASK amplitude shift keying digital communication system signal and the frequency shift keying modulation and demodulation of the VHDL code for
vhdl
- 数字信号处理的FPGA实现(Uwe Meyer-Baese)书中例子的VHDL代码-FPGA implementation of digital signal processing (Uwe Meyer-Baese) examples of VHDL code for the book
keyboardcontroller
- 键盘控制器VHDL代码 该控制器实时扫描矩阵键盘的行列，当用户有按键按下时，可以定位到对应的按键并产生一个中断信号-Keyboard controller entity -- -- The controller scans the columns, cols, by making a different column logic-0 -- therefor the inputs have to be pull-up high. It processes the input,
beta1_1
- 自已写的幅频转换vhdl代码，ad用的是tl549DA用的是5620。1602显示-To write their own amplitude-frequency converter vhdl code, ad using a tl549DA using a 5620.1602 Show
multi
- 8位乘法器，Quters编译环境VHDL代码-pluter VHDL Quters
test
- VHDL代码 键盘扫描，数码管静态移位显示，类似于计算器显示数据-VHDL code
conv.vhd
- 卷积编码的VHDL代码，公司内部资料，不是个人随便编写的-VHDL code of convolutional encoding
finalcoursework
- 用VHDL代码写的模拟微处理器核程序，有计算模块和register file 等模块，并包含测试程序，调试程序 ACTIVE HDL-Simulation with the VHDL code is written in the microprocessor core procedures, such as computing modules, and register file module, and includes test program, the debugger ACTIVE HDL
ADAPTIVEFILTER
- 采用vhdl代码描述自适应滤波器，具有很好的可参考性，和实用性-Vhdl code to describe the use of adaptive filter, can be found with a good nature and usefulness of
VHDL
- 本代码为用VHDL语言设计实现加法器、减法器、乘法器，并提供了模块图，进行了波形仿真。-This code is for the use of VHDL Language Design and Implementation of adder, subtracter, multiplier, and provides a block diagram carried out a wave simulation.
stopwatch
- 数字秒表的VHDL代码。当设计文件加载到目标器件后，设计的数字秒表从00-00-00开始计秒。，直到按下停止按键（按键开关S2）。数码管停止计秒。按下开始按键（按键开关S1），数码管继续进行计秒。按下复位按键（核心板上复位键）秒表从00-00-00重新开始计秒。-The VHDL code for digital stopwatch. When the design document loaded into the target device, the designed digital stop
vhdl
- ldpc编码的vhdl的实现，一种802.13的方式-ldpc coding vhdl implementation, a 802.13 a way
E1_to_e3_v.2.1
- E1信号到E3复用解复用VHDL代码包括时钟合成-E1 to E3 multiplexing & demultiplexing VHDL code, ，including clock synthesis
CPUdesign
- 计算机组成原理实验多时钟周期CPU设计，包含VHDL代码的设计，实验电路图，实验详细截图。-Computer component experiments designed more CPU clock cycles, including VHDL code design, test circuit, test detailed screenshots.
VHDL
- 入门的VHDL代码，非常易懂，都是入门级的程序-VHDL
8-layerelevatorrunprogram
- 用VHDL代码编写的8层电梯工作过程，有详细的注释-VHDL code is written with 8-layer lift the working process, with detailed notes
IIr
- 十阶巴特沃斯低通滤波器设计（应用时域交叉原理编写的VHDL代码）-10-order Butterworth low pass filter design (application of principles of time-domain cross-written VHDL code)
fir
- 真正意思上的fir滤波器课程设计，基于quartus II9.0的vhdl代码。有原理图输入和例化元件-The real meaning of the fir filter design program, based on quartus II9.0 the vhdl code. A schematic of components and cases
dco_12
- 是一个DCO的VHDL代码，源自Willey的博士论文，很好的一个源码，希望对各位有用。-The VHDL code is a DCO, from Willey' s doctoral thesis, a good source, and I hope you useful.
3128(vhdl)
- 里面均为用VHDL写的一些经典小程序，经过了验证均能很好的运行，一下为这些小程序的清单，希望能给大家能带来帮助： t1流水灯 t2 蜂鸣器实验 t3 拨码开关实验 t4 PWM控制LED亮度程序 t5 状态机实现流水灯 t6 静态数码管显示 t7 按键0-99计数程序 t8 红外实验 t9 0—99计数实验 t10 矩阵键盘显示 t11点阵 t12 PS2键盘识别 t13 ADC0804模拟量转化数字量实验 t14电子钟 t15 串口