搜索资源列表
fpgafft
- 用fpga实现dsp 的fft算法 其中有几个文档文件和用vhdl写的1024点的fft代码
Application_in_FPGA_design_of_Matlab_simulink
- 分析了MATLAB/Simulink 中DSP Builder 模块库在FPGA 设计中优点, 然后结合FSK 信号的产生原理,给出了如何利用DSP Builder 模块库建立FSK 信号发生器模 型,以及对FSK 信号发生器模型进行算法级仿真和生成VHDL 语言的方法,并在modelsim 中对FSK 信号发生器进行RTL 级仿真,最后介绍了在FPGA 芯片中实现FSK 信号发生器的设 计方法。
TDS510_USB2.0_DSP
- 本人现在用的TDS510 DSP仿真器的资料,准备过段时间自己做一个,里面包括VHDL程序和原理图.有兴趣可以研究一下.
经典高速乘法器IP
- 乘法器是硬件设计中的很常见也很重要的一个模块,它的VHDL硬件实现很好的解决了软件编程中做乘法速度慢的问题,在实时高速系统应用中或DSP软核或数字信号处理硬件实现算法中,经常能使用到乘法器,所以经典的高速乘法器IP 很有参考价值-Multiplier is a common and important module in hardware designing.Its VHDL addresses the low speed of multiplication in software progra
AD7982
- DSP并行读取串行接口A/D芯片的VHDL接口程序,VHDL Interface Program between DSP (parrel interface) and AD7982 (Serial interface)
XillinxFor_CKJH
- 程控交换机芯片用的VHDL语言程序, 与DSP配合完成程控交换机功能-VHDL code for tele-communication switcher in education
ADDA_control_VHDL
- VHDL语言的ADDA(模数数模置换)控制,用于程控交换机功能,与DSP和ADDA芯片配合-VHDL language ADDA (analog-to-digital digital-analog replacement) control, for program-controlled switchboard function, with the DSP and ADDA chip with
Ring_mem_VHDL
- 响铃和内存管理功能的VHDL语言,用于程控交换机中的Xillinx芯片与DSP和ADDA等芯片配合实现交换机的功能-Ringing and memory management features VHDL language, for program-controlled switchboards in Xillinx and ADDA chip and DSP chip, etc. with the function of switches realize
ad7980
- DSP并行读取串行接口A/D芯片的VHDL接口程序-VHDL Interface Program between DSP (parrel interface) and AD7980 (Serial interface)
rls
- 是二阶RLS自适应均衡的实现,采用V—LOG编写而成,是从工程中截取的 可以直接应用-Second-order RLS adaptive equalizer is the realization of the use of V-LOG prepared is intercepted from the project can be applied directly
EDA_and_VHDL
- 此压缩包是很好的vhdl教程,详细的介绍了vhdl基础,并且详细讲解了dsp设计-This package is a good tutorial vhdl, vhdl detail of the base, and detailed design on the dsp
ad
- 2812AD转换的程序,压缩包中为整个工程文件 -2812AD conversion process, compressed package for the entire project file
rs422
- 程序将通过rs422接口传进来的16bit数据转成串行输出的数据-Program will pass through the rs422 interface 16bit data transfer incoming data into a serial output
cic
- 在MATLAB2007A/SIMULINK环境下用DSP BUILDER8.0实现了五级CIC,解决了溢出问题。生成了可用的VHDL文件。- DSP BUILDER8.0 A 5 stages CIC filer is realized in MATLAB2007A/SIMULINK by using DSP Builder 8.0.The overflow problem is resulved.Useful VHDL files are generated at last.
serialports2
- 使用verilog以及VHDL编写的将串口数据转换为32位并口数据,作为FPGA和DSP接口使用(DSP型号:6205)-Use verilog and VHDL will be prepared by a 32-bit serial data into parallel data, as the FPGA, and DSP interface (DSP Model: 6205)
Df3
- fpgafft 用 实现dsp 的fft算法 其中有几个文档文件和用vhdl写的1024点 代码-fpgafft dsp with the fft algorithm to achieve a number of documents including documents and written with a vhdl code for 1024 points
project
- dsp lab programs using vhdl
UART_VHDL
- 特别适用于TI C6000 DSP扩展UART的VHDL源代码。-a VHDL source code specially for TI C6000 DSP to extend UART
dsp_test
- 利用FPGA实现DSP浮点运算,VHDL代码-FPGA implementation using floating-point DSP, VHDL code
EX28_CPLD
- Quartus编程环境下,DSP5509与CPLD的通信过程,用VHDL来编写的。-The connection between DSP and CPLD