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RS_coding_123
- RS编码的实现，包括C语言，C++，java，VHDL，DSP，matlab的RS编码实现，代码全部调是通过。-RS encoded, including the C language, C++, java, VHDL, DSPs, Matlab the RS coding, the code all the tune through.
Robust and Optimal Control by Kemin Zhou
- Embeded-SCM Develop ARM-PowerPC-ColdFire-MIPS Embeded Linux SCM VxWorks uCOS DSP program Windows CE VHDL-FPGA-Verilog Other Embeded program
DspBuilder
- 通过dsp built制成vhdl语言 -Vhdl language made by dsp built
a_vhd_16550_uart_latest.tar
- vhdl-fpga-c++-c-wireless networks-linux-verilog-cpld-arm-dsp
Image-Compress-FPGA_DSP
- 比较详细的阐述了图像压缩的原理,并基于DSP和VHDL实现该系统,最后在FPGA上通过.-More detailed exposition of the principles of image compress, and VHDL-based implementation of the system, and finally in the FPGA.
dsp320vc33_20020210.tar
- dsp 320 in vhdl.code for sram also included.
XDS100v3-Design-Kit-1.0-Setup
- 压缩包是ti xds100v3 Design kit的安装文件，安装后有原理图、PCB文件，与DSP接口采用FPGA，安装后有源码，是VHDL格式的，支持开源，降低开发成本-Compression package is ti xds100v3 Design kit installation file after installation schematics, PCB files, and DSP interface with FPGA, after installation source is
sinout
- 结合MATLAB使用dsp builder编写正弦信号发生器，然后转换成VHDL语言-dsp builder
s
- 结合MATLAB使用dsp builder编写正弦信号发生器，然后转换成VHDL语言-MATLAB dsp builder
15010120041_高瑞雪_lab2
- 在本实验中，将使用System Generator for DSP创建一个带乘法器和累加器的12-bit x 8-bit MAC（Multiplier Accumulator），并使用System Generator 的Resource Estimator块来估计资源利用率。 在仿真Simulink中的设计之后，将从该设计中生成VHDL代码和内核，并在Xilinx ISE Foundation开发软件中实现MAC。(Design, construct and verify the specifi