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usb
- 这是个USB 的VHDL 程序,进去直接双击ISE 就可以用了
Project_Navigator_Demo
- 双向控制全加器的VHDL实现 内含ISE工程文件
16×4bitFIFO
- 16×4bit的FIFO设计,VHDL语言编的的,能在ISE上仿真出来结果。
64×8bitROM
- 64×8bit 的ROM设计,VHDL语言,在ISE可以运行。
32×8bitROM
- 32×8bit的ROM设计,VHDL语言,在ISE可以运行。
dds正弦发生器代码
- 讲述了dds直接数字频率合成的基本原理,同时用VHDL语言编写dds原代码用于生成正弦波,并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果-described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for sim
FPGA-OFDM-communication-system
- 基于ofdm系统的各个模块的VHDL程序,软件是用的ISE仿真的。绝对有用。-Ofdm systems based on VHDL program of each module, the software is to use the ISE simulation. Absolutely useful.
uart
- 串口通讯 PC发送FPGA接受后回传 verilog语言-uart verilog
dds
- verilog 硬件语言实现DDS,使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
AssignmentP3
- Assignment 3 Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption styles, i.e., behavioral, dataflow and structural descr iptions. (1) Synthesize and (2) simulate these models respectively in the environment of Xilinx
fir
- 用VHDL语言设计有限脉冲响应的FIR滤波器。用户可以在Xilinx ISE环境下运行。-With VHDL language design finite impulse response of FIR filter. Users can run Xilinx ISE environment.
XiaYuWen_8_RISC_CPU
- 夏宇闻8位RISC_CPU的完整代码+TESTBENCH(已调试) modelsim工程文件,包括书中所测试的三个程序和相关数据,绝对可用~所有信号名均遵从原书。在论坛中没有找到testbench的,只有一个mcu的代码,但很多和书中的是不一样的,自己改了下下~`````大家多多支持啊~`我觉得书中也还是有些不尽如人意的地方,如clk_gen.v中clk2,clk4是没有用的,assign clk1=~clk再用clk1的negedge clk1来触发各个module也是不太好的,会使时序恶
io_lvds
- xilinx LVDS接口程序,xilinx LVDS接口程序-xilinx LVDS interface program,xilinx LVDS interface program
11_vga
- This vga controller write in vhdl xilinx ise Connect your vga monitor and view many color in moniotr-This is vga controller write in vhdl xilinx ise Connect your vga monitor and view many color in moniotr
yuelao
- 软件开发环境:ISE 7.1i 仿真环境:ModelSim SE 6.0 1. 用VHDL语言仿真歌曲刘德华的《月老》-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Using VHDL simulation language song Andy Lau' s " 月老"
honhludeng
- 软件开发环境:ISE 7.1i 仿真环境:ModelSim SE 6.0 1. 用VHDL语言仿真交通灯-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Using VHDL language simulation of traffic lights
GBJC
- 平坦度检测中的高度检测算法,使用ISE开发环境,语言为VHDL,平台是XC3S4-a vhdl_program used for flat detect
multi
- 乘法器的实现,两种方法,调用IPcore及手动编写,基于ISE软件下的VHDL语言实现-Multiplier realization of the two methods, called IPcore and manually prepared, based on the ISE software to achieve the VHDL language
skills_of_ModelSim
- modelsim使用技巧大全,包括使用教程,例子,心得等等。详细描述了如何通过modelsim进行仿真设计,是初学者需要的资料-Encyclopedia of use modelsim skills, including the use of tutorials, examples, experiences and so on. Described in detail how to design modelsim simulation is the need for information fo
pearpc-0.3.1-win32-sdl-jitc
- 基于ise平台做VHDL程序,经过很长时间积累下来的经验与大家分享-Ise-based platform to do VHDL program, after a very long time accumulated experience to share with you