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eathnet
- 百兆以太网mac和mii的vhdl源程，作IPcore的时候非常有用-Fast Ethernet MII and the VHDL source way for IPcore very useful when
DDR_allegro
- 用allegro画的ddr存储器电路。六层板设计，很好的参考资料-Allegro painting with ddr memory circuit. Six-storey plate design, very good reference
pxc3872381
- mac transmitter architecture implementatin in vhdl research paper published by nit ,bhopla.- mac transmitter architecture implementatin in vhdl research paper published by nit ,bhopla.
mac_snist
- wire less mac layer implementation using vhdl
ethernet-mac--VHDL
- 简易以太网测试仪,VHDL语言的，非常实用，有需要的可以看下-Simple Ethernet tester, VHDL language, very practical, need look
RISC-CPU-
- 用VHDL语言实现32位CPU的各种运算功能，熟悉32位CPU各模块的工作原理，熟悉流水线数据通路和控制单元的工作原理从而熟悉CPU的工作机理。-Mac circuit realization
mac_unit_vhdl
- MAC UNIT DESIGN IN VHDL-MAC UNIT DESIGN IN VHDL..
jpegencoder
- jpeg encoder in vhdl including modules MAC, Wavelet encoder, filter bank, image to text converter
ethernet 10-100 monitoring
- this is using mac IP core for ethernet connection in ISE xilinx for ethernet 10/100
CRC
- crc32 used for mac ethernet vhdl
15010120041_高瑞雪_lab2
- 在本实验中，将使用System Generator for DSP创建一个带乘法器和累加器的12-bit x 8-bit MAC（Multiplier Accumulator），并使用System Generator 的Resource Estimator块来估计资源利用率。 在仿真Simulink中的设计之后，将从该设计中生成VHDL代码和内核，并在Xilinx ISE Foundation开发软件中实现MAC。(Design, construct and verify the specifi