搜索资源列表
VHDL-Clock
- 用VHDL语言写的时钟程序。采用模块化编程。可在EPM7128芯片上下载。编译环境可用Maxplus或Quartus。-write VHDL clock procedures. Modular programming. The EPM7128 chips download. Build environment or Quartus Maxplus available.
3des-VHDL
- 3des的VHDL实现,适用于quartus环境-3des VHDL applicable to the environment quartus
8051-vhdl-code
- 单片机8051 IP内核的VHDL源码,需要的开发环境QUARTUS II 6.0。
Quartus+II+++ModelSim+SE+++后仿真+++库文件.rar
- Mentor公司的ModelSim是业界最优秀的HDL语言仿真软件,它能提供友好的仿真环境,是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术,编译仿真速度快,编译的代码与平台无关,便于保护IP核,个性化的图形界面和用户接口,为用户加快调错提供强有力的手段,是FPGA/ASIC设计的首选仿真软件。
基于VHDL语言的交通灯控制系统设计
- VHDL 交通灯控制系统 QuartusⅡ FPGA
jdcbzh.使用VHDL语言实现串并转换模块的实现
- 使用VHDL语言实现串并转换模块的实现,可在QUARTUS上实现,Use VHDL language string and conversion module, but in QUARTUS
DE2_SD_Card_Audio.DE2上SD卡的读写代码
- DE2上SD卡的读写代码,应用环境quartus ii,DE2 on SD card to read and write code
DS1307_LCD.通过IIC总线读写实时时钟DS1307
- 通过IIC总线读写实时时钟DS1307,并把时、分、秒显示在12864液晶屏上,用的CycloneII EP2C8,Quartus环境,Through the IIC bus read and write real-time clock, DS1307, and the hours, minutes and seconds displayed on the LCD screen on the 12864, used CycloneII EP2C8, Quartus environment
stopwatch.rar
- 秒表可计时,用VHDL编译的源代码,从0.1到60秒计时,解压后直接用Quartus打开project即可,Stopwatch timer can be used to compile the VHDL source code, from 0.1 to 60 seconds from time, after extracting the direct use of Quartus can open the project
ug_lpm_rom.rar
- quartus rom的生成 运用matlab生成.mif或.hex文件 载入rom表,quartus rom the use of matlab generated generation. mif or. hex file loading rom Table
DDS.rar
- 自己在Quartus下用VHDL编写的一个DDS程序。包括寄存器,累加器,波形存储器,In Quartus using VHDL procedures for the preparation of a DDS. Including the register, accumulator, waveform memory
DDS.rar
- 实现函数波形发生器的功能,内有用自己编的源代码实现的,也有用quartus的IP核实现的。,The realization of the function waveform generator function, useful for their own realization of the source code, it also uses the IP core quartus achieved.
-VHDL
- 本报告分两部分: 1 由matlab计算FIR数字滤波器的滤波系数; 2 用VHDL语言设计逻辑电路,再通过QUARTUS II 软件,将各个模块的电路封装成期间,在顶层设计中通过连线,完成整个系统。 -FIR digital filters based on VHDL
par_serial-and-serial_par-VHDL
- 并入串出移位寄存器和8路并行输出串行移位寄存器的VHDL代码,经Quartus II 5.1验证可用,String into a shift register and 8-way parallel output serial shift register of the VHDL code, the Quartus II 5.1 can be used to verify
DW8051.rar
- 一个兼容keil的8051内核,在Quartus II 8.0 上编译通过的。希望对大家有帮助!!,Keil a 8051-compatible core, the Quartus II 8.0, adopted by the compiler. We want to help! !
DDC.rar
- verilog语言实现的数字下变频设计。 在ALTERA的QUARTUS ii下实现。实用,好用。,Verilog language implementation of the digital down-conversion design. ALTERA at the implementation of QUARTUS ii. Practical, easy to use.
mux4
- 四位乘法器的VHDL语言设计,并有原理图的描述-4 Multiplier VHDL language design, and schematic descr iption of
DMA
- 针对QUARTUS的DMA的VHDL代码实现-DMA Controller Code in VHDL
Racinggame
- 赛车游戏,VHDL数字系统设计,经过QUARTUS的验证,非常好用,有非常丰富的解释,游戏有赛道,碰赛道者挂,GAME OVER-Racing game, VHDL digital system design, through verification QUARTUS, very easy to use, has a very rich interpretation, games have the track circuit are linked to touch, GAME OVER
sine-generator
- 原创:采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成,可产生正弦波。更改rom内容可改变波形-Original: Using VHDL languages sinusoidal signal generator. rom using Quartus LPM s own generation, can produce sine wave. Rom content changes can change the waveform