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verilog
- 北大微电子学系于敦山老师的课件,介绍Verilog HDL、Cadence Verilog仿真器、可综合的Verilog HDL、设计举例、自动布局布线工具、Verilog的词汇约定等内容
实用verilog代码(乘法器,触发器,FIFO等)
- 本文件包含一些实用verilog程序代码,包括乘法器,除法器,伽罗瓦域乘法器,CORDIC数字计算机的设计,异步FIFO设计,伪随机序列应用设计,RS(204,188)译码器的设计,都是可综合的。对研究这部分的朋友有一定的帮助。
以太网10-100M IP核Verilog源码
- 以太网10-100M IP核Verilog源码,可综合
veilog HDL编码规范
- 详细介绍了verilog HDL编码的注意事项和基本规范。分为可综合部分,仿真专用部分以及nc-verilog仿真环境的建立。
sha-1.rar
- 本算法基于leon2协处理器接口标准,内含testbench,在modelsim中仿真通过,在ise9.2中综合及后仿真通过。,The algorithm is based on the leon2 co-processor interface standard, including testbench, ModelSim simulation in the adoption, in ise9.2 integrated and adopted after the simulation.
dlx_verilog.rar
- 这是我个人写的DLX处理器流水线的Verilog代码,在ModelSim中仿真通过,并且在ISE中能综合!即可以下载到FPGA中运行指令,指令可以根据需要定义,也可和相应的编译器配合使用,这里给学习流水线和Verilog的朋友共享。,This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! T
mp3decoder.rar
- mp3 解码的verilog代码,通过仿真综合及验证,能够播放所有的.mp3文件。压缩包包括所有的verilog源码以及详细的文档。,mp3 decoding Verilog code, the adoption of an integrated simulation and verification, can all play. mp3 file. Compressed packet including all the Verilog source code and detailed docu
speech
- 用verilog HDL实现自相关算法! RTL级可综合代码! 通过modelsim5.6仿真和quartusii7.1综合!-Verilog HDL using auto-correlation algorithm to achieve! RTL-level code can be integrated! Through simulation and modelsim5.6 integrated quartusii7.1!
synplify_ref_ug
- Synplify指导手册,内有vhdl、verilog、system verilog等综合详细指导,非常好的进阶资料喔!虽是英文的,但来自官方,绝对可靠喔!-Synplify guide, there vhdl, verilog, system verilog detailed, comprehensive guide, very good advanced data Oh! Although in English, but from the official, absolutely relia
I2C_Slave
- I2C从设备(Slave) Verilog 代码、设计文档和使用文档,简单、适用:很方便修改工作频率,自定义寄存器接口。-I2C slave (Slave) Verilog code, design documents and user guide, simply to apply: the frequency of easy modification, customized register interface.
UART
- 语言:verilog语言 功能:通过串口控制模块,实现FPGA与串口 通信。 仿真环境:modelsim 综合环境:quartus -Language: verilog language function: through the serial port control module, FPGA and serial communication. Simulation Environment: modelsim integrated environment: quartu
collect
- 用verilog编写的max197这个AD转换的程序,在ISE综合仿真均通过。-max197, verilog
ddrsdram_verilog
- 内附doc是DDR SDRAM 参考设计文档;model包含SDRAM Verilog的模型;simulation包含verilog测试平台、modelsim工程文、设计库函数;source包含verilog源文件;synthesis包含工程的综合文件 。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM Verilog model simulation with veri
dft
- verilog语言实在点变换DFT源代码,可以配合软核或者其他CPU进行综合FFT变换,也可以单独使用生成module!-verilog language is point FFT transform source code, can tie in with the soft-core CPU, or other integrated FFT transform, it can be used to generate module!
divider16
- 16位小数除法器verilog源码,可综合的,已经仿真过。-16bit fractional numeral divider verilog source
verilog
- 一个可以综合的Verilog 7段秒表实例。上海交大微电子学院课程作业。-An example Verilog project. 7-segment
10100MIP
- 以太网10100M IP核Verilog源码(可综合)\以太网10-100M IP核Verilog源码,可综合-10100M IP Ethernet core Verilog source code (which can be integrated) \ 10-100M IP Ethernet core Verilog source code can be integrated
ca
- 基于vhdl/verilog的gps接收机伪随机码产生程序。已经过仿真综合。-Based on vhdl/verilog of the gps receiver pseudo-random code generation process. Simulation has been integrated.
sdr_c_trl_verilog
- SDRAM 控制器的Verilog代码 经过综合验证过的.无截压密码-SDRAM controller Verilog code comprehensive test after all. No cut-off pressure Password
FIFO
- 异步FIFO的实现,可综合,可验证] keywords:almost_full,full,almost_empty,empty-The realization of asynchronous FIFO can be comprehensive, verifiable] keywords: almost_full, full, almost_empty, empty