搜索资源列表
UART_verilog
- 带波特率发生器的FPGA_UART串口通信代码,使用ISE10.1综合应用过,通过计算调整两个参数baud_frequcy,baud_limit可适用于多种波特率下的UART传输-With a baud rate generator FPGA_UART serial communication code, use ISE10.1 integrated application before, by calculating the adjusted two parameters baud_frequ
Verilog-HDL-synthesis(2e)
- Verilog HDL数字设计与综合(第二版)-Digital Design and Verilog HDL synthesis
bch_verilog
- bch(255,239)编码算法的verilog实现,综合仿真通过,与matlab仿真的结果一致-bch(255,239),using verilog
digital-filter
- Verilog语言综合的固定频率的数字滤波器,用于滤除夹杂在固定频率信号上的杂波信号,包含了Quaetus工程和仿真文件。-Verilog language integrated fixed-frequency digital filter for filtering out mixed signals at a fixed frequency noise on the signal contains Quaetus engineering and simulation files.
verilog--bukezonghedeyuju
- 本文章总结了verilog语言中不可综合语句的具体情况,对于运用verilog HDL具有很大帮助-This article summarizes the verilog language is not comprehensive statement of the specific situation of great help using verilog HDL
verilog-coding-rules
- Verilog HDL可综合RTL级代码设计规范及风格-Verilog HDL RTL level code design specifications and style
verilog
- verilog数字系统设计-rtl综合测试平台与验证 书中源码-verilog Digital System Design-rtl test platform verification book source
usb
- USB的verilog IP模块,经过DesignCompiler综合验证-USB-verilog IP module, comprehensive verification through DesignCompiler
verilog-handouts
- 卡内基梅陇大学verilog讲义,包括综合,仿真,行为级建模-Carnegie Mellon University verilog handouts, including synthesis, simulation, behavioral modeling
Verilog-HDL-Digital-Design
- Verilog HDL 数字设计与综合 夏宇闻-Verilog HDL Digital Design and Xia Wen
Verilog-Hardware-description
- 本文的初衷是为了使已经对Verilog HDL有过初步了解的读者,能够进一步了解Verilog HDL与综合后的硬件之间的映射关系,从而改善代码风格,写出高效可综合的代码。-The original intention of this article to make readers already have a preliminary understanding of the Verilog HDL, and be able to learn more about the mapping bet
verilog-uart-rs232
- verilog HDL 描写的uart程序 由PC端接收然后+1返回 等等 东南大学09级4系综合课程设计-verilog HDL descr iption uart program Received by the PC side and then+1 back。 SEU..
Verilog
- 七段数码管译码器.(Verilog)[FPGA]第一个Verilog程序,七段共阴数码管摸索了好几天,终于能完成敲入代码、综合、仿真、绑定引脚至下载的全套工作了 -. 七段数码管的lookup table module SEG7_LUT ( input [3:0] iDIG, output reg [6:0] oSEG ) always@(iDIG) begin case(iDIG) 4 h1: oSEG = 7 b1111
Verilog-Language
- 可综合的verilog语法子集汇总,对于初学者来说是很好的资料。-The synthetic Verilog language subset summary, for beginners is a good information.
FPGA-Verilog-I2C
- FPGA描述I2C协议过程,采用Verilog语言编写,压缩包里含有完整的代码(已经综合仿真),仿真图-FPGA I2C protocol process descr iption, using Verilog language, compressed bundle contains the complete code (already integrated simulation), simulation map
verilog
- 自适应神经网络算法,用于障碍物检测,基于FPGA可综合实验-Adaptive neural network algorithm for obstacle detection, based on the FPGA can be integrated experiment
BCH_VLSI
- 使用HLS完成BCH编码的运算通路的设计,纯组合逻辑,对于65nm工艺可跑上1GHz。已经组合逻辑分为了多个部分,可在每一个部分之间插流水线。 附上可综合的纯RTL Code以及C++代码,以及Modelsim仿真。 可通过我的优化选项来学习如何优化HLS工具生产的代码。(BCH Encoder realized using HLS tool. Combinational logic.)
eetop.cn_Verilog HDL入门(第三版)【夏宇闻】
- veriloghdl数字设计与综合夏宇闻翻译(dgfsdghfhsgdfhgfddfghdfh)
可综合的Verilog语法(剑桥大学,影印)
- 可综合的Verilog语法(剑桥大学,影印).(A comprehensive Verilog Grammar (University of Cambridge, photocopy).)
total
- 综合应用程序,包括VGA显示,温度测量等,便于初学者掌握使用verilog HDL语言的进行综合设计和使用(Comprehensive application program, including VGA display, temperature measurement and so on, is easy for beginners to master and use Verilog HDL language for comprehensive design and use.)