搜索资源列表
DDS
- Verilog语言实现基于DDS技术的余弦信号发生器,输出位宽16Bit-Verilog language technology based on the cosine DDS signal generator, the output bit width 16Bit
ddsfinal1
- verilog语言实现的dds代码,并行通信,生成四种波形,大赛编写的代码,modelsim仿真-verilog language dds code,modelsim debug
DDS
- 关于用FPGA制作的DDS源代码。用的是verilog语言,用的是xlinx的软件-Produced with the DDS on FPGA source code. Using verilog language, using xlinx software
dds
- 采用verlog编写的tlc5615驱动程序,并利用了rom核实现了dds功能-Using verlog written tlc5615 driver, and use the rom-core functions to achieve a dds
DDS
- 能在DDS中用Verilog HDL语言实现FM,AM,FSK,ASK,PSK,结合可编程器件FGPA等等就能实现这些功能 -DDS can be used in Verilog HDL language FM, AM, FSK, ASK, PSK, etc. FGPA programmable devices can be combined to achieve these functions
DDS
- 基于verilog的DDS设计验证与仿真源代码,在quartus上实现,下载仿真成功-Based on the the the verilog DDS design verification and simulation of the source code, in quartus download simulation success
DDS-Verilog
- DDS设计的源代码 用于生成高精度的DDS程序 VERILOG-VERILOG DDS DDS program design source code used to generate high-precision
verilog dds
- 用verilog 实现dds功能,可以实现方波,三角波等波形的输出
dds
- 在altera的FPGA上实现直接数字频率合成,即用verilog实现DDS,输出正弦波形,在modelsim软件中仿真通过,已包含所有代码和工程以及二进制流文件。-The realization of direct digital frequency synthesis in the Altera FPGA, which is implemented by Verilog DDS, the output sine wave, through the simulation in Modelsim
dds(1)
- 基于DDS的信号发生器设计。DDS,FPGA,Verilog。(Design of signal generator based on DDS.DDS,FPGA,Verilog.)
DDS波形发生器
- DDS波形生成器verilog语言书写(FPGA型号cy4以上)(DDS generate verilog)
DDS
- 基于FPGA的DDS正弦信号设计,文件中有源代码(Design of DDS based on FPGA)
ex_DDS
- 基于Verilog语言实现DDS(数字频率合成器)的设计,有完整的工程设计代码和仿真脚本(Verilog language based on DDS (digital frequency synthesizer) design, there is a complete engineering design code and simulation scr ipts)
四通道DDS信号发生器
- 四通道DDS信号发生器,很好用的代码,大家一起分享(Four-channel DDS signal generator)
DDS
- 用verilog语言,在fpga上实现dds信号发生器,并在vga上显示出来(Verilog realizes DDS Signal Generator)
DDS
- 描述了verilog实现的DDS信号发生器,可以经过FPGA验证,包括了代码实现以及书写。代码可以经过altera的EDA工具进行了验证,可以实现信号发生器的基本功能。希望大家珍惜,并好好学习。(Describes the Verilog implementation of the DDS signal generator, which can be verified by FPGA, including code implementation and writing. Code can be
dds
- 基于DDS的信号源设计(包括三角波、正弦波、方波)(Design of signal source based on DDS)
DDS的VERILOG原代码
- 实现了DDS的verilog源代码,可以使用(ajhsjdhjkshfjhfsjkjksa)
DDS -changed
- DDS技术实现波形产生代码,可以编译下载学习使用!(DDS generate diagram program)
DDS
- DDS FPGA Verilog vhdl